changeset e7f403b6b76f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e7f403b6b76f
description:
base: Declare a type for context IDs
Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.
diffstat:
src/base/types.hh | 4 ++++
src/cpu/base_dyn_inst.hh | 2 +-
src/cpu/checker/thread_context.hh | 4 ++--
src/cpu/minor/exec_context.hh | 2 +-
src/cpu/o3/thread_context.hh | 2 +-
src/cpu/thread_context.cc | 6 +++---
src/cpu/thread_state.hh | 6 +++---
src/dev/arm/gic_pl390.cc | 10 +++++-----
src/dev/arm/gic_pl390.hh | 2 +-
src/dev/arm/timer_cpulocal.cc | 4 ++--
src/dev/arm/vgic.cc | 10 +++++-----
src/dev/arm/vgic.hh | 2 +-
src/dev/sinic.cc | 12 ++++++------
src/dev/sinic.hh | 8 ++++----
src/dev/sparc/iob.cc | 4 ++--
src/mem/abstract_mem.hh | 2 +-
src/mem/cache/blk.hh | 2 +-
src/mem/cache/cache_impl.hh | 3 ++-
src/mem/physical.cc | 4 ++--
src/mem/request.hh | 8 ++++----
src/mem/ruby/slicc_interface/RubyRequest.hh | 4 ++--
src/mem/ruby/system/Sequencer.cc | 6 ++----
src/sim/process.hh | 4 ++--
src/sim/system.cc | 8 ++++----
src/sim/system.hh | 7 ++++---
25 files changed, 65 insertions(+), 61 deletions(-)
diffs (truncated from 545 to 300 lines):
diff -r 2c347b12cc9c -r e7f403b6b76f src/base/types.hh
--- a/src/base/types.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/base/types.hh Fri Aug 07 09:59:13 2015 +0100
@@ -181,6 +181,10 @@
typedef int16_t ThreadID;
const ThreadID InvalidThreadID = (ThreadID)-1;
+/** Globally unique thread context ID */
+typedef int ContextID;
+const ContextID InvalidContextID = (ContextID)-1;
+
/**
* Port index/ID type, and a symbolic name for an invalid port id.
*/
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/base_dyn_inst.hh Fri Aug 07 09:59:13 2015 +0100
@@ -460,7 +460,7 @@
MasterID masterId() const { return cpu->dataMasterId(); }
/** Read this context's system-wide ID **/
- int contextId() const { return thread->contextId(); }
+ ContextID contextId() const { return thread->contextId(); }
/** Returns the fault type. */
Fault getFault() const { return fault; }
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/checker/thread_context.hh Fri Aug 07 09:59:13 2015 +0100
@@ -96,9 +96,9 @@
int cpuId() const { return actualTC->cpuId(); }
- int contextId() const { return actualTC->contextId(); }
+ ContextID contextId() const { return actualTC->contextId(); }
- void setContextId(int id)
+ void setContextId(ContextID id)
{
actualTC->setContextId(id);
checkerTC->setContextId(id);
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/minor/exec_context.hh
--- a/src/cpu/minor/exec_context.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/minor/exec_context.hh Fri Aug 07 09:59:13 2015 +0100
@@ -254,7 +254,7 @@
unsigned int readStCondFailures() const { return 0; }
void setStCondFailures(unsigned int st_cond_failures) {}
- int contextId() { return thread.contextId(); }
+ ContextID contextId() { return thread.contextId(); }
/* ISA-specific (or at least currently ISA singleton) functions */
/* X86: TLB twiddling */
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/o3/thread_context.hh Fri Aug 07 09:59:13 2015 +0100
@@ -101,7 +101,7 @@
/** Reads this CPU's Socket ID. */
virtual uint32_t socketId() const { return cpu->socketId(); }
- virtual int contextId() const { return thread->contextId(); }
+ virtual ContextID contextId() const { return thread->contextId(); }
virtual void setContextId(int id) { thread->setContextId(id); }
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/thread_context.cc
--- a/src/cpu/thread_context.cc Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/thread_context.cc Fri Aug 07 09:59:13 2015 +0100
@@ -95,9 +95,9 @@
if (id1 != id2)
panic("CPU ids don't match, one: %d, two: %d", id1, id2);
- id1 = one->contextId();
- id2 = two->contextId();
- if (id1 != id2)
+ const ContextID cid1 = one->contextId();
+ const ContextID cid2 = two->contextId();
+ if (cid1 != cid2)
panic("Context ids don't match, one: %d, two: %d", id1, id2);
diff -r 2c347b12cc9c -r e7f403b6b76f src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/cpu/thread_state.hh Fri Aug 07 09:59:13 2015 +0100
@@ -71,9 +71,9 @@
uint32_t socketId() const { return baseCpu->socketId(); }
- int contextId() const { return _contextId; }
+ ContextID contextId() const { return _contextId; }
- void setContextId(int id) { _contextId = id; }
+ void setContextId(ContextID id) { _contextId = id; }
void setThreadId(ThreadID id) { _threadId = id; }
@@ -153,7 +153,7 @@
BaseCPU *baseCpu;
// system wide HW context id
- int _contextId;
+ ContextID _contextId;
// Index of hardware thread context on the CPU that this represents.
ThreadID _threadId;
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/arm/gic_pl390.cc
--- a/src/dev/arm/gic_pl390.cc Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/arm/gic_pl390.cc Fri Aug 07 09:59:13 2015 +0100
@@ -135,7 +135,7 @@
{
Addr daddr = pkt->getAddr() - distAddr;
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
@@ -269,7 +269,7 @@
Addr daddr = pkt->getAddr() - cpuAddr;
assert(pkt->req->hasContextId());
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
assert(ctx_id < sys->numRunningContexts());
DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
@@ -356,7 +356,7 @@
Addr daddr = pkt->getAddr() - distAddr;
assert(pkt->req->hasContextId());
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
uint32_t pkt_data M5_VAR_USED;
switch (pkt->getSize())
@@ -496,7 +496,7 @@
Addr daddr = pkt->getAddr() - cpuAddr;
assert(pkt->req->hasContextId());
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
IAR iar;
DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
@@ -546,7 +546,7 @@
}
void
-Pl390::softInt(int ctx_id, SWI swi)
+Pl390::softInt(ContextID ctx_id, SWI swi)
{
switch (swi.list_type) {
case 1:
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/arm/gic_pl390.hh
--- a/src/dev/arm/gic_pl390.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/arm/gic_pl390.hh Fri Aug 07 09:59:13 2015 +0100
@@ -210,7 +210,7 @@
/** software generated interrupt
* @param data data to decode that indicates which cpus to interrupt
*/
- void softInt(int ctx_id, SWI swi);
+ void softInt(ContextID ctx_id, SWI swi);
/** See if some processor interrupt flags need to be enabled/disabled
* @param hint which set of interrupts needs to be checked
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/arm/timer_cpulocal.cc
--- a/src/dev/arm/timer_cpulocal.cc Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/arm/timer_cpulocal.cc Fri Aug 07 09:59:13 2015 +0100
@@ -75,7 +75,7 @@
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 4);
Addr daddr = pkt->getAddr() - pioAddr;
- int cpu_id = pkt->req->contextId();
+ ContextID cpu_id = pkt->req->contextId();
DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
assert(cpu_id >= 0);
assert(cpu_id < CPU_MAX);
@@ -153,7 +153,7 @@
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 4);
Addr daddr = pkt->getAddr() - pioAddr;
- int cpu_id = pkt->req->contextId();
+ ContextID cpu_id = pkt->req->contextId();
DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
assert(cpu_id >= 0);
assert(cpu_id < CPU_MAX);
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/arm/vgic.cc
--- a/src/dev/arm/vgic.cc Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/arm/vgic.cc Fri Aug 07 09:59:13 2015 +0100
@@ -90,7 +90,7 @@
{
Addr daddr = pkt->getAddr() - vcpuAddr;
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
assert(ctx_id < VGIC_CPU_MAX);
struct vcpuIntData *vid = &vcpuData[ctx_id];
@@ -134,7 +134,7 @@
{
Addr daddr = pkt->getAddr() - hvAddr;
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
@@ -228,7 +228,7 @@
{
Addr daddr = pkt->getAddr() - vcpuAddr;
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
assert(ctx_id < VGIC_CPU_MAX);
struct vcpuIntData *vid = &vcpuData[ctx_id];
@@ -275,7 +275,7 @@
{
Addr daddr = pkt->getAddr() - hvAddr;
- int ctx_id = pkt->req->contextId();
+ ContextID ctx_id = pkt->req->contextId();
DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr,
pkt->get<uint32_t>());
@@ -380,7 +380,7 @@
* This may raise a maintenance interrupt.
*/
void
-VGic::updateIntState(int ctx_id)
+VGic::updateIntState(ContextID ctx_id)
{
// @todo This should update APRs!
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/arm/vgic.hh
--- a/src/dev/arm/vgic.hh Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/arm/vgic.hh Fri Aug 07 09:59:13 2015 +0100
@@ -222,7 +222,7 @@
Tick writeVCpu(PacketPtr pkt);
Tick writeCtrl(PacketPtr pkt);
- void updateIntState(int ctx_id);
+ void updateIntState(ContextID ctx_id);
uint32_t getMISR(struct vcpuIntData *vid);
void postVInt(uint32_t cpu, Tick when);
void unPostVInt(uint32_t cpu);
diff -r 2c347b12cc9c -r e7f403b6b76f src/dev/sinic.cc
--- a/src/dev/sinic.cc Fri Aug 07 09:59:12 2015 +0100
+++ b/src/dev/sinic.cc Fri Aug 07 09:59:13 2015 +0100
@@ -152,7 +152,7 @@
void
-Device::prepareIO(int cpu, int index)
+Device::prepareIO(ContextID cpu, int index)
{
int size = virtualRegs.size();
if (index > size)
@@ -165,7 +165,7 @@
//add stats for average number of vnics busy
void
-Device::prepareRead(int cpu, int index)
+Device::prepareRead(ContextID cpu, int index)
{
using namespace Regs;
prepareIO(cpu, index);
@@ -206,7 +206,7 @@
}
void
-Device::prepareWrite(int cpu, int index)
+Device::prepareWrite(ContextID cpu, int index)
{
prepareIO(cpu, index);
}
@@ -220,7 +220,7 @@
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
- int cpu = pkt->req->contextId();
+ ContextID cpu = pkt->req->contextId();
Addr daddr = pkt->getAddr() - BARAddrs[0];
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -270,7 +270,7 @@
* IPR read of device register
Fault
-Device::iprRead(Addr daddr, int cpu, uint64_t &result)
+Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result)
{
if (!regValid(daddr))
panic("invalid address: da=%#x", daddr);
@@ -305,7 +305,7 @@
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
- int cpu = pkt->req->contextId();
+ ContextID cpu = pkt->req->contextId();
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