changeset 3815437cb231 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3815437cb231
description:
ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
diffstat:
src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 +-
src/cpu/testers/rubytest/RubyTester.hh | 4 +-
src/mem/ruby/common/Histogram.cc | 2 +-
src/mem/ruby/common/Histogram.hh | 10 ++--
src/mem/ruby/common/TypeDefines.hh | 3 -
src/mem/ruby/filters/H3BloomFilter.cc | 10 ++--
src/mem/ruby/filters/H3BloomFilter.hh | 2 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.cc | 6 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.hh | 2 +-
src/mem/ruby/network/MessageBuffer.hh | 2 +-
src/mem/ruby/profiler/AccessTraceForAddress.hh | 12 ++--
src/mem/ruby/profiler/AddressProfiler.cc | 6 +-
src/mem/ruby/profiler/AddressProfiler.hh | 2 +-
src/mem/ruby/profiler/StoreTrace.cc | 2 +-
src/mem/ruby/profiler/StoreTrace.hh | 4 +-
src/mem/ruby/structures/BankedArray.cc | 6 +-
src/mem/ruby/structures/BankedArray.hh | 8 +-
src/mem/ruby/structures/CacheMemory.cc | 45 ++++++++++-----------
src/mem/ruby/structures/CacheMemory.hh | 10 ++--
src/mem/ruby/structures/RubyMemoryControl.cc | 6 +-
src/mem/ruby/structures/RubyMemoryControl.hh | 12 ++--
src/mem/ruby/system/CacheRecorder.cc | 6 +-
src/mem/ruby/system/CacheRecorder.hh | 2 +-
src/mem/ruby/system/System.cc | 16 +++---
src/mem/ruby/system/System.hh | 8 +-
src/mem/slicc/symbols/StateMachine.py | 8 +-
26 files changed, 97 insertions(+), 101 deletions(-)
diffs (truncated from 769 to 300 lines):
diff -r 17240f381d6a -r 3815437cb231
src/cpu/testers/directedtest/RubyDirectedTester.hh
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh Fri Aug 14
19:28:43 2015 -0500
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh Fri Aug 14
19:28:43 2015 -0500
@@ -109,9 +109,9 @@
RubyDirectedTester(const RubyDirectedTester& obj);
RubyDirectedTester& operator=(const RubyDirectedTester& obj);
- uint64 m_requests_completed;
+ uint64_t m_requests_completed;
std::vector<MasterPort*> ports;
- uint64 m_requests_to_complete;
+ uint64_t m_requests_to_complete;
DirectedGenerator* generator;
};
diff -r 17240f381d6a -r 3815437cb231 src/cpu/testers/rubytest/RubyTester.hh
--- a/src/cpu/testers/rubytest/RubyTester.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/cpu/testers/rubytest/RubyTester.hh Fri Aug 14 19:28:43 2015 -0500
@@ -143,10 +143,10 @@
std::vector<Cycles> m_last_progress_vector;
int m_num_cpus;
- uint64 m_checks_completed;
+ uint64_t m_checks_completed;
std::vector<MasterPort*> writePorts;
std::vector<MasterPort*> readPorts;
- uint64 m_checks_to_complete;
+ uint64_t m_checks_to_complete;
int m_deadlock_threshold;
int m_num_writers;
int m_num_readers;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/common/Histogram.cc
--- a/src/mem/ruby/common/Histogram.cc Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/common/Histogram.cc Fri Aug 14 19:28:43 2015 -0500
@@ -84,7 +84,7 @@
}
void
-Histogram::add(int64 value)
+Histogram::add(int64_t value)
{
assert(value >= 0);
m_max = max(m_max, value);
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/common/Histogram.hh
--- a/src/mem/ruby/common/Histogram.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/common/Histogram.hh Fri Aug 14 19:28:43 2015 -0500
@@ -40,7 +40,7 @@
Histogram(int binsize = 1, uint32_t bins = 50);
~Histogram();
- void add(int64 value);
+ void add(int64_t value);
void add(Histogram& hist);
void doubleBinSize();
@@ -51,10 +51,10 @@
uint64_t size() const { return m_count; }
uint32_t getBins() const { return m_data.size(); }
int getBinSize() const { return m_binsize; }
- int64 getTotal() const { return m_sumSamples; }
+ int64_t getTotal() const { return m_sumSamples; }
uint64_t getSquaredTotal() const { return m_sumSquaredSamples; }
uint64_t getData(int index) const { return m_data[index]; }
- int64 getMax() const { return m_max; }
+ int64_t getMax() const { return m_max; }
void printWithMultiplier(std::ostream& out, double multiplier) const;
void printPercent(std::ostream& out) const;
@@ -62,12 +62,12 @@
private:
std::vector<uint64_t> m_data;
- int64 m_max; // the maximum value seen so far
+ int64_t m_max; // the maximum value seen so far
uint64_t m_count; // the number of elements added
int m_binsize; // the size of each bucket
uint32_t m_largest_bin; // the largest bin used
- int64 m_sumSamples; // the sum of all samples
+ int64_t m_sumSamples; // the sum of all samples
uint64_t m_sumSquaredSamples; // the sum of the square of all samples
double getStandardDeviation() const;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/common/TypeDefines.hh
--- a/src/mem/ruby/common/TypeDefines.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/common/TypeDefines.hh Fri Aug 14 19:28:43 2015 -0500
@@ -30,9 +30,6 @@
#ifndef TYPEDEFINES_H
#define TYPEDEFINES_H
-typedef unsigned long long uint64;
-typedef long long int64;
-
typedef unsigned int LinkID;
typedef unsigned int NodeID;
typedef unsigned int SwitchID;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/filters/H3BloomFilter.cc
--- a/src/mem/ruby/filters/H3BloomFilter.cc Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/filters/H3BloomFilter.cc Fri Aug 14 19:28:43 2015 -0500
@@ -507,8 +507,8 @@
int
H3BloomFilter::get_index(Addr addr, int i)
{
- uint64 x = makeLineAddress(addr);
- // uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
+ uint64_t x = makeLineAddress(addr);
+ // uint64_t y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
int y = hash_H3(x,i);
if (isParallel) {
@@ -519,10 +519,10 @@
}
int
-H3BloomFilter::hash_H3(uint64 value, int index)
+H3BloomFilter::hash_H3(uint64_t value, int index)
{
- uint64 mask = 1;
- uint64 val = value;
+ uint64_t mask = 1;
+ uint64_t val = value;
int result = 0;
for (int i = 0; i < 64; i++) {
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/filters/H3BloomFilter.hh
--- a/src/mem/ruby/filters/H3BloomFilter.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/filters/H3BloomFilter.hh Fri Aug 14 19:28:43 2015 -0500
@@ -68,7 +68,7 @@
private:
int get_index(Addr addr, int hashNumber);
- int hash_H3(uint64 value, int index);
+ int hash_H3(uint64_t value, int index);
std::vector<int> m_filter;
int m_filter_size;
diff -r 17240f381d6a -r 3815437cb231
src/mem/ruby/filters/MultiBitSelBloomFilter.cc
--- a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc Fri Aug 14 19:28:43
2015 -0500
+++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc Fri Aug 14 19:28:43
2015 -0500
@@ -171,7 +171,7 @@
// m_skip_bits is used to perform BitSelect after skipping some
// bits. Used to simulate BitSel hashing on larger than cache-line
// granularities
- uint64 x = (makeLineAddress(addr) >> m_skip_bits);
+ uint64_t x = (makeLineAddress(addr) >> m_skip_bits);
int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits);
//36-bit addresses, 6-bit cache lines
@@ -183,10 +183,10 @@
}
int
-MultiBitSelBloomFilter::hash_bitsel(uint64 value, int index, int jump,
+MultiBitSelBloomFilter::hash_bitsel(uint64_t value, int index, int jump,
int maxBits, int numBits)
{
- uint64 mask = 1;
+ uint64_t mask = 1;
int result = 0;
int bit, i;
diff -r 17240f381d6a -r 3815437cb231
src/mem/ruby/filters/MultiBitSelBloomFilter.hh
--- a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh Fri Aug 14 19:28:43
2015 -0500
+++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh Fri Aug 14 19:28:43
2015 -0500
@@ -68,7 +68,7 @@
private:
int get_index(Addr addr, int hashNumber);
- int hash_bitsel(uint64 value, int index, int jump, int maxBits,
+ int hash_bitsel(uint64_t value, int index, int jump, int maxBits,
int numBits);
std::vector<int> m_filter;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/network/MessageBuffer.hh
--- a/src/mem/ruby/network/MessageBuffer.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/network/MessageBuffer.hh Fri Aug 14 19:28:43 2015 -0500
@@ -184,7 +184,7 @@
int m_not_avail_count; // count the # of times I didn't have N
// slots available
- uint64 m_msg_counter;
+ uint64_t m_msg_counter;
int m_priority_rank;
const bool m_strict_fifo;
const bool m_randomization;
diff -r 17240f381d6a -r 3815437cb231
src/mem/ruby/profiler/AccessTraceForAddress.hh
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh Fri Aug 14 19:28:43
2015 -0500
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh Fri Aug 14 19:28:43
2015 -0500
@@ -67,12 +67,12 @@
private:
Addr m_addr;
- uint64 m_loads;
- uint64 m_stores;
- uint64 m_atomics;
- uint64 m_total;
- uint64 m_user;
- uint64 m_sharing;
+ uint64_t m_loads;
+ uint64_t m_stores;
+ uint64_t m_atomics;
+ uint64_t m_total;
+ uint64_t m_user;
+ uint64_t m_sharing;
Set m_touched_by;
Histogram* m_histogram_ptr;
};
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/profiler/AddressProfiler.cc
--- a/src/mem/ruby/profiler/AddressProfiler.cc Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/profiler/AddressProfiler.cc Fri Aug 14 19:28:43 2015 -0500
@@ -67,7 +67,7 @@
{
const int records_printed = 100;
- uint64 misses = 0;
+ uint64_t misses = 0;
std::vector<const AccessTraceForAddress *> sorted;
AddressMap::const_iterator i = record_map.begin();
@@ -95,8 +95,8 @@
Histogram all_records_log(-1);
// Allows us to track how many lines where touched by n processors
- std::vector<int64> m_touched_vec;
- std::vector<int64> m_touched_weighted_vec;
+ std::vector<int64_t> m_touched_vec;
+ std::vector<int64_t> m_touched_weighted_vec;
m_touched_vec.resize(num_of_sequencers+1);
m_touched_weighted_vec.resize(num_of_sequencers+1);
for (int j = 0; j < m_touched_vec.size(); j++) {
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/profiler/AddressProfiler.hh
--- a/src/mem/ruby/profiler/AddressProfiler.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/profiler/AddressProfiler.hh Fri Aug 14 19:28:43 2015 -0500
@@ -75,7 +75,7 @@
AddressProfiler(const AddressProfiler& obj);
AddressProfiler& operator=(const AddressProfiler& obj);
- int64 m_sharing_miss_counter;
+ int64_t m_sharing_miss_counter;
AddressMap m_dataAccessTrace;
AddressMap m_macroBlockAccessTrace;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/profiler/StoreTrace.cc
--- a/src/mem/ruby/profiler/StoreTrace.cc Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/profiler/StoreTrace.cc Fri Aug 14 19:28:43 2015 -0500
@@ -33,7 +33,7 @@
bool StoreTrace::s_init = false; // Total number of store lifetimes of
// all lines
-int64 StoreTrace::s_total_samples = 0; // Total number of store
+int64_t StoreTrace::s_total_samples = 0; // Total number of store
// lifetimes of all lines
Histogram* StoreTrace::s_store_count_ptr = NULL;
Histogram* StoreTrace::s_store_first_to_stolen_ptr = NULL;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/profiler/StoreTrace.hh
--- a/src/mem/ruby/profiler/StoreTrace.hh Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/profiler/StoreTrace.hh Fri Aug 14 19:28:43 2015 -0500
@@ -53,7 +53,7 @@
private:
static bool s_init;
- static int64 s_total_samples; // Total number of store lifetimes
+ static int64_t s_total_samples; // Total number of store lifetimes
// of all lines
static Histogram* s_store_count_ptr;
static Histogram* s_store_first_to_stolen_ptr;
@@ -66,7 +66,7 @@
Tick m_last_store;
int m_stores_this_interval;
- int64 m_total_samples; // Total number of store lifetimes of this line
+ int64_t m_total_samples; // Total number of store lifetimes of this line
Histogram m_store_count;
Histogram m_store_first_to_stolen;
Histogram m_store_last_to_stolen;
diff -r 17240f381d6a -r 3815437cb231 src/mem/ruby/structures/BankedArray.cc
--- a/src/mem/ruby/structures/BankedArray.cc Fri Aug 14 19:28:43 2015 -0500
+++ b/src/mem/ruby/structures/BankedArray.cc Fri Aug 14 19:28:43 2015 -0500
@@ -49,7 +49,7 @@
}
bool
-BankedArray::tryAccess(int64 idx)
+BankedArray::tryAccess(int64_t idx)
{
if (accessLatency == 0)
return true;
@@ -65,7 +65,7 @@
}
void
-BankedArray::reserve(int64 idx)
+BankedArray::reserve(int64_t idx)
{
if (accessLatency == 0)
return;
@@ -91,7 +91,7 @@
}
unsigned int
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
