changeset 3a5190683bf2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3a5190683bf2
description:
ruby: drop the [] notation for lookup function.
This is in preparation for adding a second arugment to the lookup
function for the CacheMemory class. The change to *.sm files was made
using
the following sed command:
sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 34 +++++++-------
src/mem/protocol/MESI_Three_Level-L1cache.sm | 18 +++---
src/mem/protocol/MESI_Two_Level-L1cache.sm | 52 ++++++++++----------
src/mem/protocol/MESI_Two_Level-L2cache.sm | 20 ++++----
src/mem/protocol/MESI_Two_Level-dir.sm | 24 +++++-----
src/mem/protocol/MI_example-cache.sm | 16 +++---
src/mem/protocol/MI_example-dir.sm | 20 ++++----
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 50 ++++++++++----------
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 60 ++++++++++++------------
src/mem/protocol/MOESI_CMP_directory-dir.sm | 36 +++++++-------
src/mem/protocol/MOESI_CMP_directory-dma.sm | 14 ++--
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 22 ++++----
src/mem/protocol/MOESI_CMP_token-dir.sm | 56 +++++++++++-----------
src/mem/protocol/MOESI_hammer-cache.sm | 30 ++++++------
src/mem/protocol/MOESI_hammer-dir.sm | 26 +++++-----
src/mem/slicc/parser.py | 4 -
16 files changed, 239 insertions(+), 243 deletions(-)
diffs (truncated from 1844 to 300 lines):
diff -r bf82f1f7b040 -r 3a5190683bf2
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 19:28:42
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 19:28:43
2015 -0500
@@ -145,22 +145,22 @@
// inclusive cache returns L0 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
+ Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
if(is_valid(Dcache_entry)) {
return Dcache_entry;
}
- Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
+ Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
return Icache_entry;
}
Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
+ Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
return Dcache_entry;
}
Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
+ Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
return Icache_entry;
}
@@ -189,7 +189,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
return L0Cache_State_to_permission(tbe.TBEState);
@@ -206,7 +206,7 @@
}
void functionalRead(Addr addr, Packet *pkt) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
@@ -217,7 +217,7 @@
int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
num_functional_writes := num_functional_writes +
testAndWrite(addr, tbe.DataBlk, pkt);
@@ -260,7 +260,7 @@
assert(in_msg.Dest == machineID);
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
@@ -301,7 +301,7 @@
if (is_valid(Icache_entry)) {
// The tag matches for the L0, so the L0 asks the L2 for it.
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
+ Icache_entry, TBEs.lookup(in_msg.LineAddress));
} else {
// Check to see if it is in the OTHER L0
@@ -309,19 +309,19 @@
if (is_valid(Dcache_entry)) {
// The block is in the wrong L0, put the request on the queue to
the shared L2
trigger(Event:L0_Replacement, in_msg.LineAddress,
- Dcache_entry, TBEs[in_msg.LineAddress]);
+ Dcache_entry, TBEs.lookup(in_msg.LineAddress));
}
if (Icache.cacheAvail(in_msg.LineAddress)) {
// L0 does't have the line, but we have space for it
// in the L0 so let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
+ Icache_entry, TBEs.lookup(in_msg.LineAddress));
} else {
// No room in the L0, so we need to make room in the L0
trigger(Event:L0_Replacement,
Icache.cacheProbe(in_msg.LineAddress),
getICacheEntry(Icache.cacheProbe(in_msg.LineAddress)),
- TBEs[Icache.cacheProbe(in_msg.LineAddress)]);
+ TBEs.lookup(Icache.cacheProbe(in_msg.LineAddress)));
}
}
} else {
@@ -331,7 +331,7 @@
if (is_valid(Dcache_entry)) {
// The tag matches for the L0, so the L0 ask the L1 for it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs[in_msg.LineAddress]);
+ Dcache_entry, TBEs.lookup(in_msg.LineAddress));
} else {
// Check to see if it is in the OTHER L0
@@ -339,19 +339,19 @@
if (is_valid(Icache_entry)) {
// The block is in the wrong L0, put the request on the queue to
the private L1
trigger(Event:L0_Replacement, in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
+ Icache_entry, TBEs.lookup(in_msg.LineAddress));
}
if (Dcache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it
// in the L0 let's see if the L1 has it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs[in_msg.LineAddress]);
+ Dcache_entry, TBEs.lookup(in_msg.LineAddress));
} else {
// No room in the L1, so we need to make room in the L0
trigger(Event:L0_Replacement,
Dcache.cacheProbe(in_msg.LineAddress),
getDCacheEntry(Dcache.cacheProbe(in_msg.LineAddress)),
- TBEs[Dcache.cacheProbe(in_msg.LineAddress)]);
+ TBEs.lookup(Dcache.cacheProbe(in_msg.LineAddress)));
}
}
}
@@ -489,7 +489,7 @@
check_allocate(TBEs);
assert(is_valid(cache_entry));
TBEs.allocate(address);
- set_tbe(TBEs[address]);
+ set_tbe(TBEs.lookup(address));
tbe.Dirty := cache_entry.Dirty;
tbe.DataBlk := cache_entry.DataBlk;
}
diff -r bf82f1f7b040 -r 3a5190683bf2
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Aug 14 19:28:42
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Aug 14 19:28:43
2015 -0500
@@ -161,7 +161,7 @@
// inclusive cache returns L1 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry cache_entry := static_cast(Entry, "pointer", cache[addr]);
+ Entry cache_entry := static_cast(Entry, "pointer", cache.lookup(addr));
return cache_entry;
}
@@ -186,7 +186,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return L1Cache_State_to_permission(tbe.TBEState);
@@ -203,7 +203,7 @@
}
void functionalRead(Addr addr, Packet *pkt) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
@@ -214,7 +214,7 @@
int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
num_functional_writes := num_functional_writes +
testAndWrite(addr, tbe.DataBlk, pkt);
@@ -271,7 +271,7 @@
assert(in_msg.Destination.isElement(machineID));
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
@@ -307,7 +307,7 @@
peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if (in_msg.Type == CoherenceRequestType:INV) {
if (is_valid(cache_entry) && inL0Cache(cache_entry.CacheState)) {
@@ -343,7 +343,7 @@
if (messageBufferFromL0_in.isReady()) {
peek(messageBufferFromL0_in, CoherenceMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs[in_msg.addr];
+ TBE tbe := TBEs.lookup(in_msg.addr);
if(in_msg.Class == CoherenceClass:INV_DATA) {
trigger(Event:L0_DataAck, in_msg.addr, cache_entry, tbe);
@@ -363,7 +363,7 @@
// No room in the L1, so we need to make room in the L1
Entry victim_entry :=
getCacheEntry(cache.cacheProbe(in_msg.addr));
- TBE victim_tbe := TBEs[cache.cacheProbe(in_msg.addr)];
+ TBE victim_tbe :=
TBEs.lookup(cache.cacheProbe(in_msg.addr));
if (is_valid(victim_entry) &&
inL0Cache(victim_entry.CacheState)) {
trigger(Event:L0_Invalidate_Own,
@@ -628,7 +628,7 @@
check_allocate(TBEs);
assert(is_valid(cache_entry));
TBEs.allocate(address);
- set_tbe(TBEs[address]);
+ set_tbe(TBEs.lookup(address));
tbe.Dirty := cache_entry.Dirty;
tbe.DataBlk := cache_entry.DataBlk;
}
diff -r bf82f1f7b040 -r 3a5190683bf2 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Fri Aug 14 19:28:42
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Fri Aug 14 19:28:43
2015 -0500
@@ -164,22 +164,22 @@
// inclusive cache returns L1 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
+ Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1Dcache.lookup(addr));
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
}
- Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
+ Entry L1Icache_entry := static_cast(Entry, "pointer",
L1Icache.lookup(addr));
return L1Icache_entry;
}
Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
+ Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1Dcache.lookup(addr));
return L1Dcache_entry;
}
Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
- Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
+ Entry L1Icache_entry := static_cast(Entry, "pointer",
L1Icache.lookup(addr));
return L1Icache_entry;
}
@@ -208,7 +208,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return L1Cache_State_to_permission(tbe.TBEState);
@@ -225,7 +225,7 @@
}
void functionalRead(Addr addr, Packet *pkt) {
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
@@ -236,7 +236,7 @@
int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
- TBE tbe := TBEs[addr];
+ TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
num_functional_writes := num_functional_writes +
testAndWrite(addr, tbe.DataBlk, pkt);
@@ -305,7 +305,7 @@
// cache. We should drop this request.
trigger(prefetch_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- L1Icache_entry, TBEs[in_msg.LineAddress]);
+ L1Icache_entry, TBEs.lookup(in_msg.LineAddress));
}
// Check to see if it is in the OTHER L1
@@ -315,7 +315,7 @@
// this request.
trigger(prefetch_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- L1Dcache_entry, TBEs[in_msg.LineAddress]);
+ L1Dcache_entry, TBEs.lookup(in_msg.LineAddress));
}
if (L1Icache.cacheAvail(in_msg.LineAddress)) {
@@ -323,13 +323,13 @@
// in the L1 so let's see if the L2 has it
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