changeset dfb0aa3f0649 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dfb0aa3f0649
description:
ruby: reverts to changeset: bf82f1f7b040
diffstat:
configs/ruby/Ruby.py | 5 +-
src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 +-
src/cpu/testers/rubytest/RubyTester.hh | 4 +-
src/mem/protocol/MESI_Three_Level-L0cache.sm | 62 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 18 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 83 +-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 20 +-
src/mem/protocol/MESI_Two_Level-dir.sm | 24 +-
src/mem/protocol/MI_example-cache.sm | 20 +-
src/mem/protocol/MI_example-dir.sm | 20 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 67 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 60 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 36 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 14 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 49 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 56 +-
src/mem/protocol/MOESI_hammer-cache.sm | 65 +-
src/mem/protocol/MOESI_hammer-dir.sm | 26 +-
src/mem/protocol/RubySlicc_Types.sm | 6 +-
src/mem/ruby/common/DataBlock.hh | 2 -
src/mem/ruby/common/Histogram.cc | 2 +-
src/mem/ruby/common/Histogram.hh | 10 +-
src/mem/ruby/common/SubBlock.cc | 7 +-
src/mem/ruby/common/SubBlock.hh | 7 +-
src/mem/ruby/common/TypeDefines.hh | 3 +
src/mem/ruby/filters/H3BloomFilter.cc | 10 +-
src/mem/ruby/filters/H3BloomFilter.hh | 2 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.cc | 6 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.hh | 2 +-
src/mem/ruby/network/MessageBuffer.cc | 26 +
src/mem/ruby/network/MessageBuffer.hh | 7 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 2 +-
src/mem/ruby/network/garnet/flexible-pipeline/flit.cc | 80 ++-
src/mem/ruby/network/garnet/flexible-pipeline/flit.hh | 33 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 267
++++-----
src/mem/ruby/network/simple/PerfectSwitch.hh | 4 +-
src/mem/ruby/network/simple/SimpleNetwork.cc | 22 +-
src/mem/ruby/network/simple/SimpleNetwork.hh | 8 +-
src/mem/ruby/network/simple/Switch.cc | 6 +
src/mem/ruby/network/simple/Throttle.cc | 26 +-
src/mem/ruby/network/simple/Throttle.hh | 12 +-
src/mem/ruby/profiler/AccessTraceForAddress.hh | 12 +-
src/mem/ruby/profiler/AddressProfiler.cc | 6 +-
src/mem/ruby/profiler/AddressProfiler.hh | 2 +-
src/mem/ruby/profiler/Profiler.cc | 13 +-
src/mem/ruby/profiler/Profiler.hh | 9 +-
src/mem/ruby/profiler/StoreTrace.cc | 2 +-
src/mem/ruby/profiler/StoreTrace.hh | 4 +-
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 25 -
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 24 +-
src/mem/ruby/slicc_interface/AbstractController.hh | 14 +-
src/mem/ruby/structures/AbstractReplacementPolicy.cc | 2 +-
src/mem/ruby/structures/AbstractReplacementPolicy.hh | 6 +-
src/mem/ruby/structures/BankedArray.cc | 6 +-
src/mem/ruby/structures/BankedArray.hh | 8 +-
src/mem/ruby/structures/CacheMemory.cc | 109 ++-
src/mem/ruby/structures/CacheMemory.hh | 26 +-
src/mem/ruby/structures/DirectoryMemory.cc | 2 +
src/mem/ruby/structures/DirectoryMemory.hh | 1 +
src/mem/ruby/structures/LRUPolicy.cc | 8 +-
src/mem/ruby/structures/LRUPolicy.hh | 4 +-
src/mem/ruby/structures/PseudoLRUPolicy.cc | 12 +-
src/mem/ruby/structures/PseudoLRUPolicy.hh | 6 +-
src/mem/ruby/structures/RubyMemoryControl.cc | 6 +-
src/mem/ruby/structures/RubyMemoryControl.hh | 12 +-
src/mem/ruby/system/CacheRecorder.cc | 15 +-
src/mem/ruby/system/CacheRecorder.hh | 2 +-
src/mem/ruby/system/RubySystem.py | 11 +-
src/mem/ruby/system/Sequencer.cc | 42 +-
src/mem/ruby/system/System.cc | 27 +-
src/mem/ruby/system/System.hh | 10 +-
src/mem/slicc/ast/EnumDeclAST.py | 2 +-
src/mem/slicc/ast/FormalParamAST.py | 22 +-
src/mem/slicc/ast/FuncCallExprAST.py | 17 +-
src/mem/slicc/ast/FuncDeclAST.py | 17 +-
src/mem/slicc/ast/InPortDeclAST.py | 4 +-
src/mem/slicc/ast/MethodCallExprAST.py | 21 +-
src/mem/slicc/ast/StateDeclAST.py | 4 +-
src/mem/slicc/parser.py | 10 +-
src/mem/slicc/symbols/Func.py | 35 +-
src/mem/slicc/symbols/StateMachine.py | 10 +-
81 files changed, 910 insertions(+), 841 deletions(-)
diffs (truncated from 4794 to 300 lines):
diff -r 110cce93d398 -r dfb0aa3f0649 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Fri Aug 14 19:28:44 2015 -0500
+++ b/configs/ruby/Ruby.py Wed Aug 19 10:02:01 2015 -0500
@@ -82,6 +82,9 @@
parser.add_option("--recycle-latency", type="int", default=10,
help="Recycle latency for ruby controller input buffers")
+ parser.add_option("--random_seed", type="int", default=1234,
+ help="Used for seeding the random number generator")
+
protocol = buildEnv['PROTOCOL']
exec "import %s" % protocol
eval("%s.define_options(parser)" % protocol)
@@ -231,9 +234,9 @@
if buildEnv['TARGET_ISA'] == "x86":
cpu_seq.pio_slave_port = piobus.master
- ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers
ruby.num_of_sequencers = len(cpu_sequencers)
+ ruby.random_seed = options.random_seed
# Create a backing copy of physical memory in case required
if options.access_backing_store:
diff -r 110cce93d398 -r dfb0aa3f0649
src/cpu/testers/directedtest/RubyDirectedTester.hh
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh Fri Aug 14
19:28:44 2015 -0500
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh Wed Aug 19
10:02:01 2015 -0500
@@ -109,9 +109,9 @@
RubyDirectedTester(const RubyDirectedTester& obj);
RubyDirectedTester& operator=(const RubyDirectedTester& obj);
- uint64_t m_requests_completed;
+ uint64 m_requests_completed;
std::vector<MasterPort*> ports;
- uint64_t m_requests_to_complete;
+ uint64 m_requests_to_complete;
DirectedGenerator* generator;
};
diff -r 110cce93d398 -r dfb0aa3f0649 src/cpu/testers/rubytest/RubyTester.hh
--- a/src/cpu/testers/rubytest/RubyTester.hh Fri Aug 14 19:28:44 2015 -0500
+++ b/src/cpu/testers/rubytest/RubyTester.hh Wed Aug 19 10:02:01 2015 -0500
@@ -143,10 +143,10 @@
std::vector<Cycles> m_last_progress_vector;
int m_num_cpus;
- uint64_t m_checks_completed;
+ uint64 m_checks_completed;
std::vector<MasterPort*> writePorts;
std::vector<MasterPort*> readPorts;
- uint64_t m_checks_to_complete;
+ uint64 m_checks_to_complete;
int m_deadlock_threshold;
int m_num_writers;
int m_num_readers;
diff -r 110cce93d398 -r dfb0aa3f0649
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Aug 14 19:28:44
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Wed Aug 19 10:02:01
2015 -0500
@@ -145,22 +145,22 @@
// inclusive cache returns L0 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
+ Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
if(is_valid(Dcache_entry)) {
return Dcache_entry;
}
- Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
+ Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
return Icache_entry;
}
Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache.lookup(addr));
+ Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
return Dcache_entry;
}
Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
- Entry Icache_entry := static_cast(Entry, "pointer", Icache.lookup(addr));
+ Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
return Icache_entry;
}
@@ -189,7 +189,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs.lookup(addr);
+ TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
return L0Cache_State_to_permission(tbe.TBEState);
@@ -206,7 +206,7 @@
}
void functionalRead(Addr addr, Packet *pkt) {
- TBE tbe := TBEs.lookup(addr);
+ TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
@@ -217,7 +217,7 @@
int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
- TBE tbe := TBEs.lookup(addr);
+ TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
num_functional_writes := num_functional_writes +
testAndWrite(addr, tbe.DataBlk, pkt);
@@ -260,7 +260,7 @@
assert(in_msg.Dest == machineID);
Entry cache_entry := getCacheEntry(in_msg.addr);
- TBE tbe := TBEs.lookup(in_msg.addr);
+ TBE tbe := TBEs[in_msg.addr];
if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
@@ -301,7 +301,7 @@
if (is_valid(Icache_entry)) {
// The tag matches for the L0, so the L0 asks the L2 for it.
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Icache_entry, TBEs.lookup(in_msg.LineAddress));
+ Icache_entry, TBEs[in_msg.LineAddress]);
} else {
// Check to see if it is in the OTHER L0
@@ -309,19 +309,19 @@
if (is_valid(Dcache_entry)) {
// The block is in the wrong L0, put the request on the queue to
the shared L2
trigger(Event:L0_Replacement, in_msg.LineAddress,
- Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+ Dcache_entry, TBEs[in_msg.LineAddress]);
}
if (Icache.cacheAvail(in_msg.LineAddress)) {
// L0 does't have the line, but we have space for it
// in the L0 so let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Icache_entry, TBEs.lookup(in_msg.LineAddress));
+ Icache_entry, TBEs[in_msg.LineAddress]);
} else {
// No room in the L0, so we need to make room in the L0
trigger(Event:L0_Replacement,
Icache.cacheProbe(in_msg.LineAddress),
getICacheEntry(Icache.cacheProbe(in_msg.LineAddress)),
- TBEs.lookup(Icache.cacheProbe(in_msg.LineAddress)));
+ TBEs[Icache.cacheProbe(in_msg.LineAddress)]);
}
}
} else {
@@ -331,7 +331,7 @@
if (is_valid(Dcache_entry)) {
// The tag matches for the L0, so the L0 ask the L1 for it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+ Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
// Check to see if it is in the OTHER L0
@@ -339,19 +339,19 @@
if (is_valid(Icache_entry)) {
// The block is in the wrong L0, put the request on the queue to
the private L1
trigger(Event:L0_Replacement, in_msg.LineAddress,
- Icache_entry, TBEs.lookup(in_msg.LineAddress));
+ Icache_entry, TBEs[in_msg.LineAddress]);
}
if (Dcache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it
// in the L0 let's see if the L1 has it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs.lookup(in_msg.LineAddress));
+ Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L0
trigger(Event:L0_Replacement,
Dcache.cacheProbe(in_msg.LineAddress),
getDCacheEntry(Dcache.cacheProbe(in_msg.LineAddress)),
- TBEs.lookup(Dcache.cacheProbe(in_msg.LineAddress)));
+ TBEs[Dcache.cacheProbe(in_msg.LineAddress)]);
}
}
}
@@ -459,38 +459,21 @@
}
}
- action(h_load_hit, "hd", desc="If not prefetch, notify sequencer the load
completed.") {
+ action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load
completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Dcache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk);
}
- action(h_ifetch_hit, "hi", desc="If not prefetch, notify sequencer the
ifetch completed.") {
+ action(hx_load_hit, "hx", desc="If not prefetch, notify sequencer the load
completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Icache.setMRU(cache_entry);
- sequencer.readCallback(address, cache_entry.DataBlk);
- }
-
- action(hx_load_hit, "hxd", desc="notify sequencer the load completed.") {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Dcache.setMRU(cache_entry);
- sequencer.readCallback(address, cache_entry.DataBlk, true);
- }
-
- action(hx_ifetch_hit, "hxi", desc="notify sequencer the ifetch completed.") {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Icache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that
store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk);
cache_entry.Dirty := true;
}
@@ -498,7 +481,6 @@
action(hhx_store_hit, "\hx", desc="If not prefetch, notify sequencer that
store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
@@ -507,7 +489,7 @@
check_allocate(TBEs);
assert(is_valid(cache_entry));
TBEs.allocate(address);
- set_tbe(TBEs.lookup(address));
+ set_tbe(TBEs[address]);
tbe.Dirty := cache_entry.Dirty;
tbe.DataBlk := cache_entry.DataBlk;
}
@@ -643,7 +625,7 @@
}
transition({S,E,M}, Ifetch) {
- h_ifetch_hit;
+ h_load_hit;
uu_profileInstHit;
k_popMandatoryQueue;
}
@@ -730,7 +712,7 @@
transition(Inst_IS, Data, S) {
u_writeInstToCache;
- hx_ifetch_hit;
+ hx_load_hit;
s_deallocateTBE;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
@@ -738,7 +720,7 @@
transition(Inst_IS, Data_Exclusive, E) {
u_writeInstToCache;
- hx_ifetch_hit;
+ hx_load_hit;
s_deallocateTBE;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
diff -r 110cce93d398 -r dfb0aa3f0649
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Aug 14 19:28:44
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Wed Aug 19 10:02:01
2015 -0500
@@ -161,7 +161,7 @@
// inclusive cache returns L1 entries only
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
- Entry cache_entry := static_cast(Entry, "pointer", cache.lookup(addr));
+ Entry cache_entry := static_cast(Entry, "pointer", cache[addr]);
return cache_entry;
}
@@ -186,7 +186,7 @@
}
AccessPermission getAccessPermission(Addr addr) {
- TBE tbe := TBEs.lookup(addr);
+ TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
return L1Cache_State_to_permission(tbe.TBEState);
@@ -203,7 +203,7 @@
}
void functionalRead(Addr addr, Packet *pkt) {
- TBE tbe := TBEs.lookup(addr);
+ TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
testAndRead(addr, tbe.DataBlk, pkt);
} else {
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