changeset 62544e45c0f4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=62544e45c0f4
description:
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
diffstat:
configs/common/Caches.py | 8 +-
configs/common/O3_ARM_v7a.py | 8 +-
configs/example/memcheck.py | 6 +-
configs/example/memtest.py | 6 +-
configs/splash2/cluster.py | 4 +-
configs/splash2/run.py | 4 +-
src/mem/cache/BaseCache.py | 83 -----------------------------------------
src/mem/cache/Cache.py | 89 ++++++++++++++++++++++++++++++++++++++++++++
src/mem/cache/SConscript | 2 +-
src/mem/cache/base.cc | 12 +----
src/mem/cache/base.hh | 3 +-
src/mem/cache/cache.cc | 11 ++++-
src/mem/cache/cache.hh | 3 +-
13 files changed, 122 insertions(+), 117 deletions(-)
diffs (truncated from 436 to 300 lines):
diff -r 3137d34acf29 -r 62544e45c0f4 configs/common/Caches.py
--- a/configs/common/Caches.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/common/Caches.py Fri Aug 21 07:03:23 2015 -0400
@@ -46,7 +46,7 @@
# starting point, and specific parameters can be overridden in the
# specific instantiations.
-class L1Cache(BaseCache):
+class L1Cache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
@@ -59,7 +59,7 @@
class L1_DCache(L1Cache):
pass
-class L2Cache(BaseCache):
+class L2Cache(Cache):
assoc = 8
hit_latency = 20
response_latency = 20
@@ -67,7 +67,7 @@
tgts_per_mshr = 12
write_buffers = 8
-class IOCache(BaseCache):
+class IOCache(Cache):
assoc = 8
hit_latency = 50
response_latency = 50
@@ -76,7 +76,7 @@
tgts_per_mshr = 12
forward_snoops = False
-class PageTableWalkerCache(BaseCache):
+class PageTableWalkerCache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
diff -r 3137d34acf29 -r 62544e45c0f4 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/common/O3_ARM_v7a.py Fri Aug 21 07:03:23 2015 -0400
@@ -142,7 +142,7 @@
branchPred = O3_ARM_v7a_BP()
# Instruction Cache
-class O3_ARM_v7a_ICache(BaseCache):
+class O3_ARM_v7a_ICache(Cache):
hit_latency = 1
response_latency = 1
mshrs = 2
@@ -153,7 +153,7 @@
is_read_only = True
# Data Cache
-class O3_ARM_v7a_DCache(BaseCache):
+class O3_ARM_v7a_DCache(Cache):
hit_latency = 2
response_latency = 2
mshrs = 6
@@ -164,7 +164,7 @@
# TLB Cache
# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(BaseCache):
+class O3_ARM_v7aWalkCache(Cache):
hit_latency = 4
response_latency = 4
mshrs = 6
@@ -176,7 +176,7 @@
is_read_only = True
# L2 Cache
-class O3_ARM_v7aL2(BaseCache):
+class O3_ARM_v7aL2(Cache):
hit_latency = 12
response_latency = 12
mshrs = 16
diff -r 3137d34acf29 -r 62544e45c0f4 configs/example/memcheck.py
--- a/configs/example/memcheck.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/example/memcheck.py Fri Aug 21 07:03:23 2015 -0400
@@ -152,9 +152,9 @@
numtesters += t * m
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
diff -r 3137d34acf29 -r 62544e45c0f4 configs/example/memtest.py
--- a/configs/example/memtest.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/example/memtest.py Fri Aug 21 07:03:23 2015 -0400
@@ -175,9 +175,9 @@
sys.exit(1)
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
diff -r 3137d34acf29 -r 62544e45c0f4 configs/splash2/cluster.py
--- a/configs/splash2/cluster.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/splash2/cluster.py Fri Aug 21 07:03:23 2015 -0400
@@ -137,7 +137,7 @@
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
@@ -146,7 +146,7 @@
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
diff -r 3137d34acf29 -r 62544e45c0f4 configs/splash2/run.py
--- a/configs/splash2/run.py Fri Aug 21 07:03:21 2015 -0400
+++ b/configs/splash2/run.py Fri Aug 21 07:03:23 2015 -0400
@@ -158,7 +158,7 @@
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
@@ -167,7 +167,7 @@
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
diff -r 3137d34acf29 -r 62544e45c0f4 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Fri Aug 21 07:03:21 2015 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-# Copyright (c) 2012-2013, 2015 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.params import *
-from m5.proxy import *
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from Tags import *
-
-class BaseCache(MemObject):
- type = 'BaseCache'
- cxx_header = "mem/cache/base.hh"
-
- size = Param.MemorySize("Capacity")
- assoc = Param.Unsigned("Associativity")
-
- hit_latency = Param.Cycles("Hit latency")
- response_latency = Param.Cycles("Latency for the return path on a miss");
-
- max_miss_count = Param.Counter(0,
- "Number of misses to handle before calling exit")
-
- mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
- demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
- tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
- write_buffers = Param.Unsigned(8, "Number of write buffers")
-
- forward_snoops = Param.Bool(True,
- "Forward snoops from mem side to cpu side")
- is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
-
- prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
- prefetch_on_access = Param.Bool(False,
- "Notify the hardware prefetcher on every access (not just misses)")
-
- tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
- sequential_access = Param.Bool(False,
- "Whether to access tags and data sequentially")
-
- cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
- mem_side = MasterPort("Downstream port closer to memory")
-
- addr_ranges = VectorParam.AddrRange([AllMemory],
- "Address range for the CPU-side port (to allow striping)")
-
- system = Param.System(Parent.any, "System we belong to")
diff -r 3137d34acf29 -r 62544e45c0f4 src/mem/cache/Cache.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/cache/Cache.py Fri Aug 21 07:03:23 2015 -0400
@@ -0,0 +1,89 @@
+# Copyright (c) 2012-2013, 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Andreas Hansson
+
+from m5.params import *
+from m5.proxy import *
+from MemObject import MemObject
+from Prefetcher import BasePrefetcher
+from Tags import *
+
+class BaseCache(MemObject):
+ type = 'BaseCache'
+ abstract = True
+ cxx_header = "mem/cache/base.hh"
+
+ size = Param.MemorySize("Capacity")
+ assoc = Param.Unsigned("Associativity")
+
+ hit_latency = Param.Cycles("Hit latency")
+ response_latency = Param.Cycles("Latency for the return path on a miss");
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