changeset 3c4bda5a2f66 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3c4bda5a2f66
description:
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the
replacement
policy structures with the first level caches. While functionally this
is
correct, the problem is that this requires calling findTagInSet() which
is an
expensive function. This patch removes the calls to setMRU from the
sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within
the
AbstractCacheEntry structure. Use these indicies to update the
replacement
policy structures.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 28 ++++++++++++++++---
src/mem/protocol/MESI_Two_Level-L1cache.sm | 29 ++++++++++++++------
src/mem/protocol/MI_example-cache.sm | 4 ++
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 17 ++++++++++-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 27 +++++++++++++++----
src/mem/protocol/MOESI_hammer-cache.sm | 35 +++++++++++++++++-------
src/mem/protocol/RubySlicc_Types.sm | 1 +
src/mem/ruby/structures/CacheMemory.cc | 8 +++++
src/mem/ruby/structures/CacheMemory.hh | 2 +
src/mem/ruby/system/Sequencer.cc | 12 ++-----
10 files changed, 122 insertions(+), 41 deletions(-)
diffs (truncated from 519 to 300 lines):
diff -r 672cda252689 -r 3c4bda5a2f66
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Sat Sep 05 09:35:31
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Sat Sep 05 09:35:39
2015 -0500
@@ -459,21 +459,38 @@
}
}
- action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load
completed.") {
+ action(h_load_hit, "hd", desc="If not prefetch, notify sequencer the load
completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Dcache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk);
}
- action(hx_load_hit, "hx", desc="If not prefetch, notify sequencer the load
completed.") {
+ action(h_ifetch_hit, "hi", desc="If not prefetch, notify sequencer the
ifetch completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Icache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk);
+ }
+
+ action(hx_load_hit, "hxd", desc="notify sequencer the load completed.") {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Dcache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk, true);
+ }
+
+ action(hx_ifetch_hit, "hxi", desc="notify sequencer the ifetch completed.") {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Icache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that
store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk);
cache_entry.Dirty := true;
}
@@ -481,6 +498,7 @@
action(hhx_store_hit, "\hx", desc="If not prefetch, notify sequencer that
store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
@@ -625,7 +643,7 @@
}
transition({S,E,M}, Ifetch) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileInstHit;
k_popMandatoryQueue;
}
@@ -712,7 +730,7 @@
transition(Inst_IS, Data, S) {
u_writeInstToCache;
- hx_load_hit;
+ hx_ifetch_hit;
s_deallocateTBE;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
@@ -720,7 +738,7 @@
transition(Inst_IS, Data_Exclusive, E) {
u_writeInstToCache;
- hx_load_hit;
+ hx_ifetch_hit;
s_deallocateTBE;
o_popIncomingResponseQueue;
kd_wakeUpDependents;
diff -r 672cda252689 -r 3c4bda5a2f66 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Sat Sep 05 09:35:31
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Sat Sep 05 09:35:39
2015 -0500
@@ -810,36 +810,47 @@
sequencer.invalidateSC(address);
}
- action(h_load_hit, "h",
- desc="If not prefetch, notify sequencer the load completed.")
+ action(h_load_hit, "hd",
+ desc="Notify sequencer the load completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk);
}
- action(hx_load_hit, "hx",
- desc="If not prefetch, notify sequencer the load completed.")
+ action(h_ifetch_hit, "hi", desc="Notify sequencer the instruction fetch
completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk);
+ }
+
+ action(hx_load_hit, "hx", desc="Notify sequencer the load completed.")
+ {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
- action(hh_store_hit, "\h",
- desc="If not prefetch, notify sequencer that store completed.")
+ action(hh_store_hit, "\h", desc="Notify sequencer that store completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk);
cache_entry.Dirty := true;
}
- action(hhx_store_hit, "\hx",
- desc="If not prefetch, notify sequencer that store completed.")
+ action(hhx_store_hit, "\hx", desc="Notify sequencer that store completed.")
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
@@ -1081,7 +1092,7 @@
}
transition({S,E,M}, Ifetch) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileInstHit;
k_popMandatoryQueue;
}
diff -r 672cda252689 -r 3c4bda5a2f66 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Sat Sep 05 09:35:31 2015 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Sat Sep 05 09:35:39 2015 -0500
@@ -352,6 +352,7 @@
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
+ cacheMemory.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, false);
}
@@ -359,6 +360,7 @@
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
+ cacheMemory.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, true,
machineIDToMachineType(in_msg.Sender));
}
@@ -367,6 +369,7 @@
action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
+ cacheMemory.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, false);
}
@@ -374,6 +377,7 @@
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
+ cacheMemory.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, true,
machineIDToMachineType(in_msg.Sender));
}
diff -r 672cda252689 -r 3c4bda5a2f66
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Sep 05 09:35:31
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Sep 05 09:35:39
2015 -0500
@@ -635,21 +635,32 @@
}
}
- action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
+ action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk);
+ }
+
+ action(h_ifetch_hit, "hi", desc="Notify the sequencer about ifetch
completion.") {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk);
}
action(hx_load_hit, "hx", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk);
cache_entry.Dirty := true;
}
@@ -657,6 +668,8 @@
action(xx_store_hit, "\xx", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
@@ -964,7 +977,7 @@
}
transition({S, SM, O, OM, MM, MM_W, M, M_W}, Ifetch) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileInstHit;
k_popMandatoryQueue;
}
diff -r 672cda252689 -r 3c4bda5a2f66 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Sep 05 09:35:31
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Sep 05 09:35:39
2015 -0500
@@ -1282,12 +1282,22 @@
}
}
-
- action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
+ action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
+ sequencer.readCallback(address, cache_entry.DataBlk, false,
+ MachineType:L1Cache);
+ }
+
+ action(h_ifetch_hit, "hi", desc="Notify sequencer the load completed.") {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ address, cache_entry.DataBlk);
+
+ L1Icache.setMRU(cache_entry);
sequencer.readCallback(address, cache_entry.DataBlk, false,
MachineType:L1Cache);
}
@@ -1297,6 +1307,8 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.readCallback(address, cache_entry.DataBlk,
isExternalHit(address, in_msg.Sender),
machineIDToMachineType(in_msg.Sender));
@@ -1308,6 +1320,7 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
+ L1Dcache.setMRU(cache_entry);
sequencer.writeCallback(address, cache_entry.DataBlk, false,
MachineType:L1Cache);
cache_entry.Dirty := true;
@@ -1319,6 +1332,8 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
+ L1Icache.setMRU(address);
+ L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk,
isExternalHit(address, in_msg.Sender),
machineIDToMachineType(in_msg.Sender));
@@ -1700,7 +1715,7 @@
}
transition({S, SM, S_L, SM_L}, Ifetch) {
- h_load_hit;
+ h_ifetch_hit;
uu_profileInstHit;
k_popMandatoryQueue;
}
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