Is AMD okay that these patches are getting pushed before they can get further code up for review? It would be a good idea to quiesce ruby component interface changes like this and setMRU until they can get code posted (assuming it can be in reasonably soon).
Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Wisconsin - Madison http://www.cs.utexas.edu/~hestness > On Sep 5, 2015, at 11:16 AM, Nilay Vaish <[email protected]> wrote: > > changeset ee2fcca7b58a in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=ee2fcca7b58a > description: > ruby: declare all protocol message buffers as parameters > > MessageBuffer is a SimObject now. There were protocols that still declared > some of the message buffers are variables of the controller, but not as > input > parameters. Special handling was required for these variables in the SLICC > compiler. This patch changes this. Now all message buffers are declared > as > input parameters. > > diffstat: > > src/mem/protocol/MESI_Three_Level-L0cache.sm | 6 +- > src/mem/protocol/MESI_Two_Level-L1cache.sm | 11 ++- > src/mem/protocol/MESI_Two_Level-dir.sm | 4 +- > src/mem/protocol/MESI_Two_Level-dma.sm | 2 +- > src/mem/protocol/MI_example-cache.sm | 5 +- > src/mem/protocol/MI_example-dir.sm | 3 +- > src/mem/protocol/MI_example-dma.sm | 5 +- > src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 8 +- > src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 3 +- > src/mem/protocol/MOESI_CMP_directory-dir.sm | 3 +- > src/mem/protocol/MOESI_CMP_directory-dma.sm | 4 +- > src/mem/protocol/MOESI_CMP_token-L1cache.sm | 4 +- > src/mem/protocol/MOESI_CMP_token-dir.sm | 3 +- > src/mem/protocol/MOESI_CMP_token-dma.sm | 5 +- > src/mem/protocol/MOESI_hammer-cache.sm | 12 +--- > src/mem/protocol/MOESI_hammer-dir.sm | 6 +- > src/mem/protocol/MOESI_hammer-dma.sm | 2 +- > src/mem/protocol/Network_test-cache.sm | 5 +- > src/mem/slicc/symbols/StateMachine.py | 65 +++++++----------------- > 19 files changed, 61 insertions(+), 95 deletions(-) > > diffs (truncated from 564 to 300 lines): > > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MESI_Three_Level-L0cache.sm > --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Sep 04 13:14:03 > 2015 -0400 > +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Sat Sep 05 09:34:24 > 2015 -0500 > @@ -39,10 +39,10 @@ > > // To this node's L0 cache FROM the network > MessageBuffer * bufferFromL1, network="From"; > + > + // Message queue between this controller and the processor > + MessageBuffer * mandatoryQueue; > { > - // Message queue between this controller and the processor > - MessageBuffer mandatoryQueue; > - > // STATES > state_declaration(State, desc="Cache states", default="L0Cache_State_I") { > // Base states > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MESI_Two_Level-L1cache.sm > --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Sat Sep 05 09:34:24 2015 > -0500 > @@ -61,10 +61,13 @@ > // a L2 bank -> this L1 > MessageBuffer * responseToL1Cache, network="From", virtual_network="1", > vnet_type="response"; > + > + // Request Buffer for prefetches > + MessageBuffer * optionalQueue; > + > + // Buffer for requests generated by the processor core. > + MessageBuffer * mandatoryQueue; > { > - // Request Buffer for prefetches > - MessageBuffer optionalQueue; > - > // STATES > state_declaration(State, desc="Cache states", default="L1Cache_State_I") { > // Base states > @@ -151,8 +154,6 @@ > > TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; > > - MessageBuffer mandatoryQueue; > - > int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; > > void set_cache_entry(AbstractCacheEntry a); > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MESI_Two_Level-dir.sm > --- a/src/mem/protocol/MESI_Two_Level-dir.sm Fri Sep 04 13:14:03 2015 -0400 > +++ b/src/mem/protocol/MESI_Two_Level-dir.sm Sat Sep 05 09:34:24 2015 -0500 > @@ -37,6 +37,8 @@ > vnet_type="response"; > MessageBuffer * responseFromDir, network="To", virtual_network="1", > vnet_type="response"; > + > + MessageBuffer * responseFromMemory; > { > // STATES > state_declaration(State, desc="Directory states", > default="Directory_State_I") { > @@ -182,8 +184,6 @@ > (type == CoherenceRequestType:GETX); > } > > - MessageBuffer responseFromMemory; > - > // ** OUT_PORTS ** > out_port(responseNetwork_out, ResponseMsg, responseFromDir); > > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MESI_Two_Level-dma.sm > --- a/src/mem/protocol/MESI_Two_Level-dma.sm Fri Sep 04 13:14:03 2015 -0400 > +++ b/src/mem/protocol/MESI_Two_Level-dma.sm Sat Sep 05 09:34:24 2015 -0500 > @@ -35,6 +35,7 @@ > vnet_type="response"; > MessageBuffer * requestToDir, network="To", virtual_network="0", > vnet_type="request"; > + MessageBuffer * mandatoryQueue; > { > state_declaration(State, desc="DMA states", default="DMA_State_READY") { > READY, AccessPermission:Invalid, desc="Ready to accept a new request"; > @@ -49,7 +50,6 @@ > Ack, desc="DMA write to memory completed"; > } > > - MessageBuffer mandatoryQueue; > State cur_state; > > State getState(Addr addr) { > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MI_example-cache.sm > --- a/src/mem/protocol/MI_example-cache.sm Fri Sep 04 13:14:03 2015 -0400 > +++ b/src/mem/protocol/MI_example-cache.sm Sat Sep 05 09:34:24 2015 -0500 > @@ -44,6 +44,8 @@ > vnet_type="forward"; > MessageBuffer * responseToCache, network="From", virtual_network="4", > vnet_type="response"; > + > + MessageBuffer * mandatoryQueue; > { > // STATES > state_declaration(State, desc="Cache states") { > @@ -76,9 +78,6 @@ > } > > // STRUCTURE DEFINITIONS > - > - MessageBuffer mandatoryQueue; > - > // CacheEntry > structure(Entry, desc="...", interface="AbstractCacheEntry") { > State CacheState, desc="cache state"; > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MI_example-dir.sm > --- a/src/mem/protocol/MI_example-dir.sm Fri Sep 04 13:14:03 2015 -0400 > +++ b/src/mem/protocol/MI_example-dir.sm Sat Sep 05 09:34:24 2015 -0500 > @@ -43,6 +43,7 @@ > vnet_type="request"; > MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", > vnet_type="request"; > + MessageBuffer * responseFromMemory; > { > // STATES > state_declaration(State, desc="Directory states", > default="Directory_State_I") { > @@ -195,8 +196,6 @@ > return num_functional_writes; > } > > - MessageBuffer responseFromMemory; > - > // ** OUT_PORTS ** > out_port(forwardNetwork_out, RequestMsg, forwardFromDir); > out_port(responseNetwork_out, ResponseMsg, responseFromDir); > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MI_example-dma.sm > --- a/src/mem/protocol/MI_example-dma.sm Fri Sep 04 13:14:03 2015 -0400 > +++ b/src/mem/protocol/MI_example-dma.sm Sat Sep 05 09:34:24 2015 -0500 > @@ -35,6 +35,7 @@ > vnet_type="response"; > MessageBuffer * requestToDir, network="To", virtual_network="0", > vnet_type="request"; > + MessageBuffer * mandatoryQueue; > { > state_declaration(State, desc="DMA states", default="DMA_State_READY") { > READY, AccessPermission:Invalid, desc="Ready to accept a new request"; > @@ -49,14 +50,14 @@ > Ack, desc="DMA write to memory completed"; > } > > - MessageBuffer mandatoryQueue; > State cur_state; > > State getState(Addr addr) { > return cur_state; > } > + > void setState(Addr addr, State state) { > - cur_state := state; > + cur_state := state; > } > > AccessPermission getAccessPermission(Addr addr) { > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MOESI_CMP_directory-L1cache.sm > --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Fri Sep 04 13:14:03 > 2015 -0400 > +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Sep 05 09:34:24 > 2015 -0500 > @@ -51,6 +51,10 @@ > // a L2 bank -> this L1 > MessageBuffer * responseToL1Cache, network="From", virtual_network="2", > vnet_type="response"; > + > + MessageBuffer * triggerQueue; > + > + MessageBuffer * mandatoryQueue; > { > // STATES > state_declaration(State, desc="Cache states", default="L1Cache_State_I") { > @@ -134,8 +138,6 @@ > void set_tbe(TBE b); > void unset_tbe(); > > - MessageBuffer mandatoryQueue, abstract_chip_ptr="true"; > - > TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; > TimerTable useTimerTable; > int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; > @@ -254,8 +256,6 @@ > } > } > > - MessageBuffer triggerQueue; > - > // ** OUT_PORTS ** > > out_port(requestNetwork_out, RequestMsg, requestFromL1Cache); > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MOESI_CMP_directory-L2cache.sm > --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Fri Sep 04 13:14:03 > 2015 -0400 > +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sat Sep 05 09:34:24 > 2015 -0500 > @@ -48,6 +48,7 @@ > MessageBuffer * responseToL2Cache, network="From", virtual_network="2", > vnet_type="response"; // a local L1 || mod-directory -> this L2 bank > > + MessageBuffer * triggerQueue; > { > // STATES > state_declaration(State, desc="L2 Cache states", default="L2Cache_State_I") > { > @@ -565,8 +566,6 @@ > return num_functional_writes; > } > > - MessageBuffer triggerQueue; > - > out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache); > out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache); > out_port(responseNetwork_out, ResponseMsg, responseFromL2Cache); > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MOESI_CMP_directory-dir.sm > --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Sat Sep 05 09:34:24 2015 > -0500 > @@ -42,6 +42,7 @@ > MessageBuffer * responseFromDir, network="To", virtual_network="2", > vnet_type="response"; // Dir -> mod-L2 bank > > + MessageBuffer * responseFromMemory; > { > // STATES > state_declaration(State, desc="Directory states", > default="Directory_State_I") { > @@ -220,8 +221,6 @@ > return false; > } > > - MessageBuffer responseFromMemory; > - > // ** OUT_PORTS ** > out_port(forwardNetwork_out, RequestMsg, forwardFromDir); > out_port(responseNetwork_out, ResponseMsg, responseFromDir); > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MOESI_CMP_directory-dma.sm > --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Sat Sep 05 09:34:24 2015 > -0500 > @@ -40,6 +40,8 @@ > MessageBuffer * respToDir, network="To", virtual_network="2", > vnet_type="dmaresponse"; > > + MessageBuffer * mandatoryQueue; > + MessageBuffer * triggerQueue; > { > state_declaration(State, desc="DMA states", default="DMA_State_READY") { > READY, AccessPermission:Invalid, desc="Ready to accept a new request"; > @@ -69,8 +71,6 @@ > bool isPresent(Addr); > } > > - MessageBuffer mandatoryQueue; > - MessageBuffer triggerQueue; > TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs"; > State cur_state; > > diff -r 61b329833f74 -r ee2fcca7b58a > src/mem/protocol/MOESI_CMP_token-L1cache.sm > --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Sep 05 09:34:24 2015 > -0500 > @@ -61,7 +61,6 @@ > MessageBuffer * requestFromL1Cache, network="To", virtual_network="1", > vnet_type="request"; > > - > // To this node's L1 cache FROM the network > > // a L2 bank -> this L1 > @@ -73,6 +72,7 @@ > MessageBuffer * requestToL1Cache, network="From", virtual_network="1", > vnet_type="request"; > > + MessageBuffer * mandatoryQueue; > { > // STATES > state_declaration(State, desc="Cache states", default="L1Cache_State_I") { > @@ -194,8 +194,6 @@ > > TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; > > - MessageBuffer mandatoryQueue, abstract_chip_ptr="true"; > - > bool starving, default="false"; > int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; > > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MOESI_CMP_token-dir.sm > --- a/src/mem/protocol/MOESI_CMP_token-dir.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Sat Sep 05 09:34:24 2015 > -0500 > @@ -61,6 +61,7 @@ > MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", > vnet_type="request"; > > + MessageBuffer * responseFromMemory; > { > // STATES > state_declaration(State, desc="Directory states", > default="Directory_State_O") { > @@ -266,8 +267,6 @@ > return num_functional_writes; > } > > - MessageBuffer responseFromMemory; > - > // ** OUT_PORTS ** > out_port(responseNetwork_out, ResponseMsg, responseFromDir); > out_port(persistentNetwork_out, PersistentMsg, persistentFromDir); > diff -r 61b329833f74 -r ee2fcca7b58a src/mem/protocol/MOESI_CMP_token-dma.sm > --- a/src/mem/protocol/MOESI_CMP_token-dma.sm Fri Sep 04 13:14:03 2015 > -0400 > +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Sat Sep 05 09:34:24 2015 > -0500 > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
