Hello all
I was looking at CC register implementation in gem5 and found out that the rename-stage of o3 cpu does not look at the number of free ccPhyregs while determining if pipeline should stall or not. The number of free entries only in integer and float physical register files is checked. In O3CPU.py, I found a comment which says "In typical real machines, CC regs are not explicitly renamed (it's a side effect of int reg renaming), so they should never be the bottleneck here." I do not understand this comment completely. How is the renaming of CC registers handled in real machines, if they are not explicitly renamed like int/float regs? Every instruction that has "completed" execution, is not yet "committed" and affects the condition codes would need to update the condition codes somewhere. If it's not done through explicit cc register renaming, what is the mechanism used in actual systems? Is there any difference between how ARM and x86 handle this? Regards Lokesh Jindal _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
