changeset 6da33e720481 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6da33e720481
description:
ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no
longer
maintain pointers to clock objects. Functions in these structures have
been
changed to take as input current time in Tick. Similarly, these
structures
will not operate on Cycle valued latencies for different operations.
The
corresponding functions would need to be provided with these latencies
by
components invoking the relevant functions. These latencies should
also be
in Ticks.
I felt the need for these changes while trying to speed up ruby. The
ultimate
aim is to eliminate Consumer class and replace it with an EventManager
object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the
object and
function to be invoked.
In hindsight, it seems I should have done this while I was moving away
from use
of a single global clock in the memory system. That change led to
introduction
of clock objects that replaced the global clock object. It never
crossed my
mind that having clock object pointers is not a good design. And now I
really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 14 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 16 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 20 +-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 21 +-
src/mem/protocol/MESI_Two_Level-dir.sm | 18 +-
src/mem/protocol/MESI_Two_Level-dma.sm | 9 +-
src/mem/protocol/MI_example-cache.sm | 16 +-
src/mem/protocol/MI_example-dir.sm | 19 +-
src/mem/protocol/MI_example-dma.sm | 11 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 33 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 24 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 16 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 13 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 75
++++---
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 17 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 43 ++-
src/mem/protocol/MOESI_CMP_token-dma.sm | 10 +-
src/mem/protocol/MOESI_hammer-cache.sm | 17 +-
src/mem/protocol/MOESI_hammer-dir.sm | 25 +-
src/mem/protocol/MOESI_hammer-dma.sm | 10 +-
src/mem/protocol/Network_test-cache.sm | 5 +-
src/mem/protocol/Network_test-dir.sm | 16 +-
src/mem/protocol/RubySlicc_Defines.sm | 2 +-
src/mem/protocol/RubySlicc_Exports.sm | 1 +
src/mem/protocol/RubySlicc_Types.sm | 12 +-
src/mem/ruby/network/MessageBuffer.cc | 104
++++-----
src/mem/ruby/network/MessageBuffer.hh | 57 +----
src/mem/ruby/network/MessageBuffer.py | 1 -
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 16 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 15 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 12 +-
src/mem/ruby/network/simple/SimpleNetwork.py | 6 -
src/mem/ruby/network/simple/Switch.cc | 13 -
src/mem/ruby/network/simple/Throttle.cc | 20 +-
src/mem/ruby/slicc_interface/AbstractController.cc | 13 +-
src/mem/ruby/structures/TBETable.hh | 4 +-
src/mem/ruby/structures/TimerTable.cc | 17 +-
src/mem/ruby/structures/TimerTable.hh | 21 +-
src/mem/ruby/system/DMASequencer.cc | 5 +-
src/mem/ruby/system/RubyPort.cc | 1 -
src/mem/ruby/system/Sequencer.cc | 2 +-
src/mem/slicc/ast/EnqueueStatementAST.py | 5 +-
src/mem/slicc/ast/ObjDeclAST.py | 2 +
src/mem/slicc/ast/PeekStatementAST.py | 2 +-
src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 +-
src/mem/slicc/symbols/StateMachine.py | 19 +-
46 files changed, 382 insertions(+), 418 deletions(-)
diffs (truncated from 2748 to 300 lines):
diff -r 8647458d421d -r 6da33e720481
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Wed Sep 16 11:59:55
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Wed Sep 16 11:59:56
2015 -0500
@@ -135,6 +135,8 @@
TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Cycles ticksToCycles(Tick t);
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
@@ -255,7 +257,7 @@
// Messages for this L0 cache from the L1 cache
in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) {
- if (messgeBuffer_in.isReady()) {
+ if (messgeBuffer_in.isReady(clockEdge())) {
peek(messgeBuffer_in, CoherenceMsg, block_on="addr") {
assert(in_msg.Dest == machineID);
@@ -289,7 +291,7 @@
// Mandatory Queue betweens Node's CPU and it's L0 caches
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank =
0) {
- if (mandatoryQueue_in.isReady()) {
+ if (mandatoryQueue_in.isReady(clockEdge())) {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in
D-cache
@@ -513,17 +515,19 @@
}
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
- mandatoryQueue_in.dequeue();
+ mandatoryQueue_in.dequeue(clockEdge());
}
action(l_popRequestQueue, "l",
desc="Pop incoming request queue and profile the delay within this
virtual network") {
- profileMsgDelay(2, messgeBuffer_in.dequeue());
+ Tick delay := messgeBuffer_in.dequeue(clockEdge());
+ profileMsgDelay(2, ticksToCycles(delay));
}
action(o_popIncomingResponseQueue, "o",
desc="Pop Incoming Response queue and profile the delay within this
virtual network") {
- profileMsgDelay(1, messgeBuffer_in.dequeue());
+ Tick delay := messgeBuffer_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
diff -r 8647458d421d -r 6da33e720481
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Wed Sep 16 11:59:55
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Wed Sep 16 11:59:56
2015 -0500
@@ -151,6 +151,8 @@
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
+ Tick clockEdge();
+ Cycles ticksToCycles(Tick t);
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
@@ -266,7 +268,7 @@
// Response From the L2 Cache to this L1 cache
in_port(responseNetwork_in, ResponseMsg, responseFromL2, rank = 3) {
- if (responseNetwork_in.isReady()) {
+ if (responseNetwork_in.isReady(clockEdge())) {
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID));
@@ -303,7 +305,7 @@
// Request to this L1 cache from the shared L2
in_port(requestNetwork_in, RequestMsg, requestFromL2, rank = 2) {
- if(requestNetwork_in.isReady()) {
+ if(requestNetwork_in.isReady(clockEdge())) {
peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));
Entry cache_entry := getCacheEntry(in_msg.addr);
@@ -340,7 +342,7 @@
// Requests to this L1 cache from the L0 cache.
in_port(messageBufferFromL0_in, CoherenceMsg, bufferFromL0, rank = 0) {
- if (messageBufferFromL0_in.isReady()) {
+ if (messageBufferFromL0_in.isReady(clockEdge())) {
peek(messageBufferFromL0_in, CoherenceMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
@@ -634,17 +636,19 @@
}
action(k_popL0RequestQueue, "k", desc="Pop mandatory queue.") {
- messageBufferFromL0_in.dequeue();
+ messageBufferFromL0_in.dequeue(clockEdge());
}
action(l_popL2RequestQueue, "l",
desc="Pop incoming request queue and profile the delay within this
virtual network") {
- profileMsgDelay(2, requestNetwork_in.dequeue());
+ Tick delay := requestNetwork_in.dequeue(clockEdge());
+ profileMsgDelay(2, ticksToCycles(delay));
}
action(o_popL2ResponseQueue, "o",
desc="Pop Incoming Response queue and profile the delay within this
virtual network") {
- profileMsgDelay(1, responseNetwork_in.dequeue());
+ Tick delay := responseNetwork_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
diff -r 8647458d421d -r 6da33e720481 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Wed Sep 16 11:59:55
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Wed Sep 16 11:59:56
2015 -0500
@@ -156,6 +156,8 @@
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
+ Tick clockEdge();
+ Cycles ticksToCycles(Tick t);
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
@@ -296,7 +298,7 @@
// searches of all entries in the queue, not just the head msg. All
// msgs in the structure can be invalidated if a demand miss matches.
in_port(optionalQueue_in, RubyRequest, optionalQueue, desc="...", rank = 3) {
- if (optionalQueue_in.isReady()) {
+ if (optionalQueue_in.isReady(clockEdge())) {
peek(optionalQueue_in, RubyRequest) {
// Instruction Prefetch
if (in_msg.Type == RubyRequestType:IFETCH) {
@@ -373,7 +375,7 @@
// Response L1 Network - response msg to this L1 cache
in_port(responseL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {
- if (responseL1Network_in.isReady()) {
+ if (responseL1Network_in.isReady(clockEdge())) {
peek(responseL1Network_in, ResponseMsg, block_on="addr") {
assert(in_msg.Destination.isElement(machineID));
@@ -413,7 +415,7 @@
// Request InterChip network - request from this L1 cache to the shared L2
in_port(requestL1Network_in, RequestMsg, requestToL1Cache, rank = 1) {
- if(requestL1Network_in.isReady()) {
+ if(requestL1Network_in.isReady(clockEdge())) {
peek(requestL1Network_in, RequestMsg, block_on="addr") {
assert(in_msg.Destination.isElement(machineID));
@@ -439,7 +441,7 @@
// Mandatory Queue betweens Node's CPU and it's L1 caches
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank =
0) {
- if (mandatoryQueue_in.isReady()) {
+ if (mandatoryQueue_in.isReady(clockEdge())) {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in
D-cache
@@ -866,17 +868,19 @@
}
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
- mandatoryQueue_in.dequeue();
+ mandatoryQueue_in.dequeue(clockEdge());
}
action(l_popRequestQueue, "l",
desc="Pop incoming request queue and profile the delay within this virtual
network") {
- profileMsgDelay(2, requestL1Network_in.dequeue());
+ Tick delay := requestL1Network_in.dequeue(clockEdge());
+ profileMsgDelay(2, ticksToCycles(delay));
}
action(o_popIncomingResponseQueue, "o",
desc="Pop Incoming Response queue and profile the delay within this
virtual network") {
- profileMsgDelay(1, responseL1Network_in.dequeue());
+ Tick delay := responseL1Network_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
@@ -963,7 +967,7 @@
}
action(pq_popPrefetchQueue, "\pq", desc="Pop the prefetch request queue") {
- optionalQueue_in.dequeue();
+ optionalQueue_in.dequeue(clockEdge());
}
action(mp_markPrefetched, "mp", desc="Write data from response queue to
cache") {
diff -r 8647458d421d -r 6da33e720481 src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Wed Sep 16 11:59:55
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Wed Sep 16 11:59:56
2015 -0500
@@ -148,6 +148,10 @@
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Tick cyclesToTicks(Cycles c);
+ Cycles ticksToCycles(Tick t);
+
void set_cache_entry(AbstractCacheEntry a);
void unset_cache_entry();
void set_tbe(TBE a);
@@ -285,7 +289,7 @@
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
- if(L1unblockNetwork_in.isReady()) {
+ if(L1unblockNetwork_in.isReady(clockEdge())) {
peek(L1unblockNetwork_in, ResponseMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
@@ -307,7 +311,7 @@
// Response L2 Network - response msg to this particular L2 bank
in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
- if (responseL2Network_in.isReady()) {
+ if (responseL2Network_in.isReady(clockEdge())) {
peek(responseL2Network_in, ResponseMsg) {
// test wether it's from a local L1 or an off chip source
assert(in_msg.Destination.isElement(machineID));
@@ -348,7 +352,7 @@
// L1 Request
in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
- if(L1RequestL2Network_in.isReady()) {
+ if(L1RequestL2Network_in.isReady(clockEdge())) {
peek(L1RequestL2Network_in, RequestMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
@@ -604,15 +608,18 @@
}
action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
- profileMsgDelay(0, L1RequestL2Network_in.dequeue());
+ Tick delay := L1RequestL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
- profileMsgDelay(0, L1unblockNetwork_in.dequeue());
+ Tick delay := L1unblockNetwork_in.dequeue(clockEdge());
+ profileMsgDelay(0, ticksToCycles(delay));
}
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
- profileMsgDelay(1, responseL2Network_in.dequeue());
+ Tick delay := responseL2Network_in.dequeue(clockEdge());
+ profileMsgDelay(1, ticksToCycles(delay));
}
action(m_writeDataToCache, "m", desc="Write data from response queue to
cache") {
@@ -769,7 +776,7 @@
}
action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
- responseL2Network_in.recycle();
+ responseL2Network_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
}
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
diff -r 8647458d421d -r 6da33e720481 src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm Wed Sep 16 11:59:55 2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm Wed Sep 16 11:59:56 2015 -0500
@@ -98,6 +98,8 @@
// ** OBJECTS **
TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+ Tick clockEdge();
+ Tick cyclesToTicks(Cycles c);
void set_tbe(TBE tbe);
void unset_tbe();
void wakeUpBuffers(Addr a);
@@ -190,7 +192,7 @@
// ** IN_PORTS **
in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) {
- if (requestNetwork_in.isReady()) {
+ if (requestNetwork_in.isReady(clockEdge())) {
peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));
if (isGETRequest(in_msg.Type)) {
@@ -210,7 +212,7 @@
}
in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) {
- if (responseNetwork_in.isReady()) {
+ if (responseNetwork_in.isReady(clockEdge())) {
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID));
if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
@@ -227,7 +229,7 @@
// off-chip memory request/response is done
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