changeset 75c1e564a725 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=75c1e564a725
description:
ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make
changes to
print statements. So the addresses which were being printed in hex
earlier
along with their line address, were now being printed in decimals.
This patch
adds a function printAddress(Addr) that can be used to print the
address in hex
along with the lines address. This function has been put to use in
some of the
places. At other places, change has been made to print just the
address in
hex.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 8 ++++----
src/mem/protocol/MESI_Three_Level-L1cache.sm | 10 +++++-----
src/mem/protocol/MESI_Two_Level-L1cache.sm | 20 ++++++++++----------
src/mem/protocol/MESI_Two_Level-L2cache.sm | 10 +++++-----
src/mem/protocol/MI_example-cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 4 ++--
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 22 +++++++++++-----------
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 14 +++++++-------
src/mem/protocol/MOESI_hammer-cache.sm | 2 +-
src/mem/ruby/common/Address.cc | 10 ++++++++++
src/mem/ruby/common/Address.hh | 1 +
src/mem/ruby/network/MessageBuffer.cc | 4 ++--
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 6 +++---
src/mem/ruby/slicc_interface/AbstractController.cc | 2 +-
src/mem/ruby/slicc_interface/RubyRequest.cc | 6 +++---
src/mem/ruby/structures/CacheMemory.cc | 22 +++++++++++-----------
src/mem/ruby/structures/DirectoryMemory.cc | 4 ++--
src/mem/ruby/structures/Prefetcher.cc | 10 +++++-----
src/mem/ruby/system/RubySystem.cc | 4 ++--
src/mem/ruby/system/Sequencer.cc | 4 ++--
src/mem/slicc/symbols/StateMachine.py | 8 ++++----
src/mem/slicc/symbols/Type.py | 6 +++++-
22 files changed, 97 insertions(+), 82 deletions(-)
diffs (truncated from 809 to 300 lines):
diff -r 2a1a21f79047 -r 75c1e564a725
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -369,7 +369,7 @@
out_msg.Class := CoherenceClass:GETS;
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -386,7 +386,7 @@
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -402,7 +402,7 @@
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -438,7 +438,7 @@
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to
the processor") {
if (send_evictions) {
- DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}
diff -r 2a1a21f79047 -r 75c1e564a725
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -392,7 +392,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -409,7 +409,7 @@
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -425,7 +425,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@@ -580,7 +580,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
+ DPRINTF(RubySlicc, "%#x\n", address);
}
}
@@ -592,7 +592,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
+ DPRINTF(RubySlicc, "%#x\n", address);
}
}
diff -r 2a1a21f79047 -r 75c1e564a725 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -528,7 +528,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -545,7 +545,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -562,7 +562,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -585,7 +585,7 @@
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
}
}
@@ -600,7 +600,7 @@
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -620,7 +620,7 @@
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -637,7 +637,7 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@@ -759,7 +759,7 @@
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to
the processor") {
if (send_evictions) {
- DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}
@@ -790,7 +790,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
+ DPRINTF(RubySlicc, "%#x\n", address);
}
}
@@ -802,7 +802,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
+ DPRINTF(RubySlicc, "%#x\n", address);
}
}
diff -r 2a1a21f79047 -r 75c1e564a725 src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -174,7 +174,7 @@
void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+ DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %#x\n",
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
@@ -267,7 +267,7 @@
return Event:L1_PUTX_old;
}
} else {
- DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
+ DPRINTF(RubySlicc, "address: %#x, Request Type: %s\n", addr, type);
error("Invalid L1 forwarded request type");
}
}
@@ -293,7 +293,7 @@
peek(L1unblockNetwork_in, ResponseMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
- DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
+ DPRINTF(RubySlicc, "Addr: %#x State: %s Sender: %s Type: %s Dest:
%s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
@@ -357,7 +357,7 @@
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
- DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
+ DPRINTF(RubySlicc, "Addr: %#x State: %s Req: %s Type: %s Dest: %s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Requestor, in_msg.Type, in_msg.Destination);
@@ -546,7 +546,7 @@
out_msg.Destination.add(tbe.L1_GetX_ID);
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := cache_entry.DataBlk;
- DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
+ DPRINTF(RubySlicc, "Address: %#x, Destination: %s, DataBlock: %s\n",
out_msg.addr, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
diff -r 2a1a21f79047 -r 75c1e564a725 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Fri Sep 18 13:27:47 2015 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Fri Sep 18 13:27:47 2015 -0500
@@ -396,7 +396,7 @@
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to
the processor") {
if (send_evictions) {
- DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}
diff -r 2a1a21f79047 -r 75c1e564a725
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -514,7 +514,7 @@
out_msg.Acks := in_msg.Acks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
- DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.addr);
+ DPRINTF(RubySlicc, "Sending data to L2: %#x\n", in_msg.addr);
}
else {
enqueue(responseNetwork_out, ResponseMsg, request_latency) {
@@ -889,7 +889,7 @@
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to
the processor") {
if (send_evictions) {
- DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}
diff -r 2a1a21f79047 -r 75c1e564a725
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Fri Sep 18 13:27:47
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Fri Sep 18 13:27:47
2015 -0500
@@ -797,7 +797,7 @@
out_msg.Dirty := false;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@@ -814,7 +814,7 @@
out_msg.Acks := tbe.Local_GETX_IntAcks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@@ -864,7 +864,7 @@
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@@ -883,7 +883,7 @@
out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
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