----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3033/#review7232 -----------------------------------------------------------
src/arch/arm/isa/formats/neon64.isa (lines 90 - 95) <http://reviews.gem5.org/r/3033/#comment6160> Can I see how the template is being used? src/arch/arm/isa/insts/neon64.isa (lines 3372 - 3374) <http://reviews.gem5.org/r/3033/#comment6159> We can drop this. - Nilay Vaish On Aug. 12, 2015, 5:38 p.m., Curtis Dunham wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3033/ > ----------------------------------------------------------- > > (Updated Aug. 12, 2015, 5:38 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > The decoder is responsible for splitting instructions in micro > operations (uops). Given that different micro architectures may split > operations differently, this patch allows to specify which micro > architecture each isa implements, so different cores in the system can > split instructions differently, also decoupling uop splitting > (microArch) from ISA (Arch). This is done making the decodification > calls templates that receive a type 'DecoderFlavour' that maps the > name of the operation to the class that implements it. This way there > is only one selection point (converting the command line enum to the > appropriate DecodeFeatures object). In addition, there is no explicit > code replication: template instantiation hides that, and the compiler > should be able to resolve a number of things at compile-time. > > > Diffs > ----- > > src/arch/arm/isa/includes.isa b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/isa/insts/neon64.isa b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/mips/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/power/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/sparc/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/x86/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/cpu/o3/fetch_impl.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/alpha/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/ArmISA.py b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/decoder.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/decoder.cc b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/isa.hh b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/isa.cc b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/isa/formats/aarch64.isa > b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > src/arch/arm/isa/formats/neon64.isa > b998b5a6c5f59b41e0c0997ca1bebe37717ad551 > > Diff: http://reviews.gem5.org/r/3033/diff/ > > > Testing > ------- > > > Thanks, > > Curtis Dunham > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
