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Review request for Default. Repository: gem5 Description ------- Changeset 11139:6433ce0b920e --------------------------- ruby: combine RubyPort and Sequencer and rename as FirstLevelController This patch move the file RubyPort.* to FirstLevelController.*. Then, it copies the contents of Sequencer.* to FirstLevelController.*. Finally, it renames RubyPort and Sequencer to FirstLevelController and adjusts line lengths where ever execeeded. There are two reasons for this change: * I find this FirstLevelController abstraction better than having separate RubyPort and Sequencer. With the FirstLevelController class, we are trying to imply the functionality is common to all controllers that are directly attached to the cores. Earlier, it appeared as if there are two components between the core and the actual first level controller. Now the first level controllers in slicc would inherit from this new FirstLevelController class and we would directly connect the controller to the core, instead of going through the sequencer. * The combined entity would allow us to make some changes that would ultimately improve ruby's performance significantly. Diffs ----- src/mem/protocol/MESI_Two_Level-L1cache.sm 5d38dc2f7d66 src/mem/protocol/MESI_Two_Level-dma.sm 5d38dc2f7d66 src/mem/protocol/MI_example-cache.sm 5d38dc2f7d66 src/mem/protocol/MI_example-dma.sm 5d38dc2f7d66 src/mem/protocol/MOESI_CMP_directory-L1cache.sm 5d38dc2f7d66 src/mem/protocol/MOESI_CMP_directory-dma.sm 5d38dc2f7d66 src/mem/protocol/MOESI_CMP_token-L1cache.sm 5d38dc2f7d66 src/mem/protocol/MOESI_CMP_token-dma.sm 5d38dc2f7d66 src/mem/protocol/MOESI_hammer-cache.sm 5d38dc2f7d66 src/mem/protocol/MOESI_hammer-dma.sm 5d38dc2f7d66 src/mem/protocol/Network_test-cache.sm 5d38dc2f7d66 src/mem/protocol/RubySlicc_Exports.sm 5d38dc2f7d66 src/mem/protocol/RubySlicc_Types.sm 5d38dc2f7d66 src/mem/ruby/SConscript 5d38dc2f7d66 src/mem/ruby/profiler/Profiler.cc 5d38dc2f7d66 src/mem/ruby/slicc_interface/AbstractController.hh 5d38dc2f7d66 src/mem/ruby/slicc_interface/AbstractController.cc 5d38dc2f7d66 src/mem/ruby/slicc_interface/AbstractDMAController.hh PRE-CREATION src/mem/ruby/slicc_interface/AbstractDMAController.cc PRE-CREATION src/mem/ruby/slicc_interface/Controller.py 5d38dc2f7d66 src/mem/ruby/slicc_interface/FirstLevelController.hh PRE-CREATION src/mem/ruby/slicc_interface/FirstLevelController.cc PRE-CREATION src/mem/ruby/slicc_interface/SConscript 5d38dc2f7d66 src/mem/ruby/system/CacheRecorder.hh 5d38dc2f7d66 src/mem/ruby/system/CacheRecorder.cc 5d38dc2f7d66 src/mem/ruby/system/DMASequencer.hh 5d38dc2f7d66 src/mem/ruby/system/DMASequencer.cc 5d38dc2f7d66 src/mem/ruby/system/RubyPort.hh 5d38dc2f7d66 src/mem/ruby/system/RubyPort.cc 5d38dc2f7d66 src/mem/ruby/system/RubyPortProxy.hh 5d38dc2f7d66 src/mem/ruby/system/RubySystem.cc 5d38dc2f7d66 src/mem/ruby/system/RubySystem.py 5d38dc2f7d66 src/mem/ruby/system/SConscript 5d38dc2f7d66 src/mem/ruby/system/Sequencer.hh 5d38dc2f7d66 src/mem/ruby/system/Sequencer.cc 5d38dc2f7d66 src/mem/ruby/system/Sequencer.py 5d38dc2f7d66 src/mem/slicc/symbols/StateMachine.py 5d38dc2f7d66 tests/configs/pc-simple-timing-ruby.py 5d38dc2f7d66 configs/example/fs.py 5d38dc2f7d66 configs/ruby/MESI_Three_Level.py 5d38dc2f7d66 configs/ruby/MESI_Two_Level.py 5d38dc2f7d66 configs/ruby/MI_example.py 5d38dc2f7d66 configs/ruby/MOESI_CMP_directory.py 5d38dc2f7d66 configs/ruby/MOESI_CMP_token.py 5d38dc2f7d66 configs/ruby/MOESI_hammer.py 5d38dc2f7d66 configs/ruby/Network_test.py 5d38dc2f7d66 configs/ruby/Ruby.py 5d38dc2f7d66 src/mem/protocol/MESI_Three_Level-L0cache.sm 5d38dc2f7d66 Diff: http://reviews.gem5.org/r/3134/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
