changeset f918d72dbc02 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f918d72dbc02
description:
util: Fix minor issues in DRAM sweep scripts
This patch fixes a few issues in the sweep scripts, bringing them
up-to-date with the latest memory configs and options.
diffstat:
configs/dram/sweep.py | 11 ++++++-----
util/dram_sweep_plot.py | 2 +-
2 files changed, 7 insertions(+), 6 deletions(-)
diffs (40 lines):
diff -r 5d38dc2f7d66 -r f918d72dbc02 configs/dram/sweep.py
--- a/configs/dram/sweep.py Thu Sep 24 08:41:24 2015 -0500
+++ b/configs/dram/sweep.py Fri Sep 25 06:45:50 2015 -0400
@@ -81,11 +81,11 @@
# at the moment we stay with the default open-adaptive page policy,
# and address mapping
-# start with the system itself, using a multi-layer 1.5 GHz
-# crossbar, delivering 64 bytes / 5 cycles (one header cycle)
-# which amounts to 19.2 GByte/s per layer and thus per port
-system = System(membus = IOXBar(width = 16))
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+# start with the system itself, using a multi-layer 2.0 GHz
+# crossbar, delivering 64 bytes / 3 cycles (one header cycle)
+# which amounts to 42.7 GByte/s per layer and thus per port
+system = System(membus = IOXBar(width = 32))
+system.clk_domain = SrcClockDomain(clock = '2.0GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
@@ -100,6 +100,7 @@
# generator
options.mem_channels = 1
options.external_memory_system = 0
+options.tlm_memory = 0
MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM
diff -r 5d38dc2f7d66 -r f918d72dbc02 util/dram_sweep_plot.py
--- a/util/dram_sweep_plot.py Thu Sep 24 08:41:24 2015 -0500
+++ b/util/dram_sweep_plot.py Fri Sep 25 06:45:50 2015 -0400
@@ -116,7 +116,7 @@
if match:
peak_bw.append(float(match.groups(0)[0]))
- match = re.match(".*averagePower\s+(\d+\.\d+)\s+#.*", line)
+ match = re.match(".*averagePower\s+(\d+\.?\d*)\s+#.*", line)
if match:
avg_pwr.append(float(match.groups(0)[0]))
stats.close()
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