changeset 0fd6976303bc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0fd6976303bc
description:
cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores +
Non-SMT
cores) caused failures due to the CPU id assignment logic. The comment
about thread assignment (worrying about core 0 not having tid 0) seems
not to be valid given that our configuration scripts initialize them in
order.
This removes that constraint so a heterogenously threaded sytem can
work.
diffstat:
src/cpu/base.cc | 16 ++++++----------
src/sim/System.py | 3 +++
src/sim/system.cc | 1 +
src/sim/system.hh | 1 +
4 files changed, 11 insertions(+), 10 deletions(-)
diffs (66 lines):
diff -r 939f3919b108 -r 0fd6976303bc src/cpu/base.cc
--- a/src/cpu/base.cc Tue Sep 29 09:28:26 2015 -0500
+++ b/src/cpu/base.cc Wed Sep 30 11:14:19 2015 -0500
@@ -436,21 +436,17 @@
void
BaseCPU::registerThreadContexts()
{
+ assert(system->multiThread || numThreads == 1);
+
ThreadID size = threadContexts.size();
for (ThreadID tid = 0; tid < size; ++tid) {
ThreadContext *tc = threadContexts[tid];
- /** This is so that contextId and cpuId match where there is a
- * 1cpu:1context relationship. Otherwise, the order of registration
- * could affect the assignment and cpu 1 could have context id 3, for
- * example. We may even want to do something like this for SMT so that
- * cpu 0 has the lowest thread contexts and cpu N has the highest, but
- * I'll just do this for now
- */
- if (numThreads == 1)
+ if (system->multiThread) {
+ tc->setContextId(system->registerThreadContext(tc));
+ } else {
tc->setContextId(system->registerThreadContext(tc, _cpuId));
- else
- tc->setContextId(system->registerThreadContext(tc));
+ }
if (!FullSystem)
tc->getProcessPtr()->assignThreadContext(tc->contextId());
diff -r 939f3919b108 -r 0fd6976303bc src/sim/System.py
--- a/src/sim/System.py Tue Sep 29 09:28:26 2015 -0500
+++ b/src/sim/System.py Wed Sep 30 11:14:19 2015 -0500
@@ -99,6 +99,9 @@
"Address to mask loading binaries with")
load_offset = Param.UInt64(0, "Address to offset loading binaries with")
+ multi_thread = Param.Bool(False,
+ "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
+
# Dynamic voltage and frequency handler for the system, disabled by default
# Provide list of domains that need to be controlled by the handler
dvfs_handler = DVFSHandler()
diff -r 939f3919b108 -r 0fd6976303bc src/sim/system.cc
--- a/src/sim/system.cc Tue Sep 29 09:28:26 2015 -0500
+++ b/src/sim/system.cc Wed Sep 30 11:14:19 2015 -0500
@@ -80,6 +80,7 @@
System::System(Params *p)
: MemObject(p), _systemPort("system_port", this),
_numContexts(0),
+ multiThread(p->multi_thread),
pagePtr(0),
init_param(p->init_param),
physProxy(_systemPort, p->cache_line_size),
diff -r 939f3919b108 -r 0fd6976303bc src/sim/system.hh
--- a/src/sim/system.hh Tue Sep 29 09:28:26 2015 -0500
+++ b/src/sim/system.hh Wed Sep 30 11:14:19 2015 -0500
@@ -196,6 +196,7 @@
std::vector<ThreadContext *> threadContexts;
int _numContexts;
+ const bool multiThread;
ThreadContext *getThreadContext(ContextID tid)
{
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