Thanks for making this change, Andreas. It's good to know the tests I added actually worked!
I'll update the text of the tutorial with this change soon. Thanks, Jason On Thu, Oct 1, 2015 at 3:07 AM Andreas Hansson <[email protected]> wrote: > changeset fce93f1c885b in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=fce93f1c885b > description: > config: Fix 'learning gem5' configs after SMT push > > This patch updates the 'learning gem5' example scripts to match the > recent push of the SMT patches. > > diffstat: > > configs/learning_gem5/part1/simple.py | 6 +++--- > configs/learning_gem5/part1/two_level.py | 6 +++--- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diffs (32 lines): > > diff -r 20bbfe5b2b86 -r fce93f1c885b configs/learning_gem5/part1/simple.py > --- a/configs/learning_gem5/part1/simple.py Wed Sep 30 15:21:55 2015 > -0500 > +++ b/configs/learning_gem5/part1/simple.py Thu Oct 01 04:07:15 2015 > -0400 > @@ -70,9 +70,9 @@ > # For x86 only, make sure the interrupts are connected to the memory > # Note: these are directly connected to the memory bus and are not cached > if m5.defines.buildEnv['TARGET_ISA'] == "x86": > - system.cpu.interrupts.pio = system.membus.master > - system.cpu.interrupts.int_master = system.membus.slave > - system.cpu.interrupts.int_slave = system.membus.master > + system.cpu.interrupts[0].pio = system.membus.master > + system.cpu.interrupts[0].int_master = system.membus.slave > + system.cpu.interrupts[0].int_slave = system.membus.master > > # Create a DDR3 memory controller and connect it to the membus > system.mem_ctrl = DDR3_1600_x64() > diff -r 20bbfe5b2b86 -r fce93f1c885b > configs/learning_gem5/part1/two_level.py > --- a/configs/learning_gem5/part1/two_level.py Wed Sep 30 15:21:55 2015 > -0500 > +++ b/configs/learning_gem5/part1/two_level.py Thu Oct 01 04:07:15 2015 > -0400 > @@ -120,9 +120,9 @@ > # For x86 only, make sure the interrupts are connected to the memory > # Note: these are directly connected to the memory bus and are not cached > if m5.defines.buildEnv['TARGET_ISA'] == "x86": > - system.cpu.interrupts.pio = system.membus.master > - system.cpu.interrupts.int_master = system.membus.slave > - system.cpu.interrupts.int_slave = system.membus.master > + system.cpu.interrupts[0].pio = system.membus.master > + system.cpu.interrupts[0].int_master = system.membus.slave > + system.cpu.interrupts[0].int_slave = system.membus.master > > # Connect the system up to the membus > system.system_port = system.membus.slave > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
