changeset a37dda0f0202 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a37dda0f0202
description:
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
diffstat:
tests/SConscript | 2
+-
tests/configs/base_config.py | 10
+-
tests/configs/o3-timing-mt.py | 57
+
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini | 765
++++++
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr | 2
+
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout | 15
+
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt | 1141
++++++++++
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini | 765
------
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr | 2
-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 15
-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 1141
----------
tests/quick/se/01.hello-2T-smt/test.py | 2
-
12 files changed, 1988 insertions(+), 1929 deletions(-)
diffs (truncated from 3999 to 300 lines):
diff -r d660f0d38e3b -r a37dda0f0202 tests/SConscript
--- a/tests/SConscript Fri Oct 02 01:04:12 2015 -0400
+++ b/tests/SConscript Mon Oct 05 13:13:23 2015 -0500
@@ -357,7 +357,7 @@
configs += ['simple-atomic', 'simple-atomic-mp',
'simple-timing', 'simple-timing-mp',
'minor-timing', 'minor-timing-mp',
- 'o3-timing', 'o3-timing-mp',
+ 'o3-timing', 'o3-timing-mt', 'o3-timing-mp',
'rubytest', 'memtest', 'memtest-filter',
'tgen-simple-mem', 'tgen-dram-ctrl']
diff -r d660f0d38e3b -r a37dda0f0202 tests/configs/base_config.py
--- a/tests/configs/base_config.py Fri Oct 02 01:04:12 2015 -0400
+++ b/tests/configs/base_config.py Mon Oct 05 13:13:23 2015 -0500
@@ -58,7 +58,8 @@
__metaclass__ = ABCMeta
def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
- cpu_class=TimingSimpleCPU, num_cpus=1, checker=False,
+ cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
+ checker=False,
mem_size=None):
"""Initialize a simple base system.
@@ -74,11 +75,13 @@
self.mem_class = mem_class
self.cpu_class = cpu_class
self.num_cpus = num_cpus
+ self.num_threads = num_threads
self.checker = checker
def create_cpus(self, cpu_clk_domain):
"""Return a list of CPU objects to add to a system."""
- cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
+ cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
+ numThreads=self.num_threads,
cpu_id=i)
for i in range(self.num_cpus) ]
if self.checker:
@@ -187,7 +190,8 @@
def create_system(self):
system = System(physmem = self.mem_class(),
membus = SystemXBar(),
- mem_mode = self.mem_mode)
+ mem_mode = self.mem_mode,
+ multi_thread = (self.num_threads > 1))
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
self.init_system(system)
diff -r d660f0d38e3b -r a37dda0f0202 tests/configs/o3-timing-mt.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/o3-timing-mt.py Mon Oct 05 13:13:23 2015 -0500
@@ -0,0 +1,57 @@
+# Copyright (c) 2013, 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+from m5.objects import *
+from m5.defines import buildEnv
+from base_config import *
+from arm_generic import *
+from O3_ARM_v7a import O3_ARM_v7a_3
+
+# If we are running ARM regressions, use a more sensible CPU
+# configuration. This makes the results more meaningful, and also
+# increases the coverage of the regressions.
+if buildEnv['TARGET_ISA'] == "arm":
+ root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ cpu_class=O3_ARM_v7a_3,
+ num_threads=2).create_root()
+else:
+ root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ cpu_class=DerivO3CPU,
+ num_threads=2).create_root()
diff -r d660f0d38e3b -r a37dda0f0202
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
Mon Oct 05 13:13:23 2015 -0500
@@ -0,0 +1,765 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem
voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=DerivO3CPU
+children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache
toL2Bus tracer workload0 workload1
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu.branchPred
+cachePorts=200
+checker=Null
+clk_domain=system.cpu_clk_domain
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
+fetchQueueSize=32
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa0 system.cpu.isa1
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysCCRegs=0
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=2
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbWidth=8
+workload=system.cpu.workload0 system.cpu.workload1
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=TournamentBP
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=2
+
+[system.cpu.dcache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_read_only=false
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
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