> On Oct. 10, 2015, 9:21 p.m., Nilay Vaish wrote: > > src/arch/power/types.hh, lines 92-101 > > <http://reviews.gem5.org/r/3147/diff/1/?file=50061#file50061line92> > > > > Why do we need to add stuff to the std namespace?
We are using custom implementation of std::hash<X>::operator() for various reasons. The way to do so is to add the hash class to namespace std. Note that this has always been done this way. This patch does _not_ change any behaviour. > On Oct. 10, 2015, 9:21 p.m., Nilay Vaish wrote: > > src/mem/ruby/structures/CacheMemory.cc, line 116 > > <http://reviews.gem5.org/r/3147/diff/1/?file=50183#file50183line116> > > > > So what type would the compiler infer here? Do you know when will > > the compiler choose a const_iterator (underlying element cannot change) > > and when will it choose a const iterator (iterator itself cannot > > change)? Do we really care? If you worry I can change it back to an explicit type, but I must confess I really do not see the point in this instance. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3147/#review7348 ----------------------------------------------------------- On Oct. 8, 2015, 2:29 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3147/ > ----------------------------------------------------------- > > (Updated Oct. 8, 2015, 2:29 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11164:4f94ad14561f > --------------------------- > misc: Remove redundant compiler-specific defines > > This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap > (and similar) abstractions, as these are no longer needed with gcc 4.7 > and clang 3.1 as minimum compiler versions. > > > Diffs > ----- > > src/sim/sim_events.hh c81401cf5cc2 > src/sim/sim_object.hh c81401cf5cc2 > src/sim/system.hh c81401cf5cc2 > src/sim/ticked_object.hh c81401cf5cc2 > src/sim/voltage_domain.hh c81401cf5cc2 > src/mem/coherent_xbar.hh c81401cf5cc2 > src/mem/comm_monitor.hh c81401cf5cc2 > src/mem/dram_ctrl.hh c81401cf5cc2 > src/mem/dramsim2.hh c81401cf5cc2 > src/mem/mem_checker.hh c81401cf5cc2 > src/mem/multi_level_page_table.hh c81401cf5cc2 > src/mem/packet_queue.hh c81401cf5cc2 > src/mem/page_table.hh c81401cf5cc2 > src/mem/physical.hh c81401cf5cc2 > src/mem/probes/base.hh c81401cf5cc2 > src/mem/probes/mem_trace.hh c81401cf5cc2 > src/mem/probes/stack_dist.hh c81401cf5cc2 > src/mem/ruby/common/Address.hh c81401cf5cc2 > src/mem/ruby/profiler/AddressProfiler.hh c81401cf5cc2 > src/mem/ruby/profiler/Profiler.hh c81401cf5cc2 > src/mem/ruby/structures/CacheMemory.hh c81401cf5cc2 > src/mem/ruby/structures/CacheMemory.cc c81401cf5cc2 > src/mem/ruby/structures/PerfectCacheMemory.hh c81401cf5cc2 > src/mem/ruby/structures/PersistentTable.hh c81401cf5cc2 > src/mem/ruby/structures/RubyMemoryControl.hh c81401cf5cc2 > src/mem/ruby/structures/TBETable.hh c81401cf5cc2 > src/mem/ruby/system/CacheRecorder.hh c81401cf5cc2 > src/mem/ruby/system/DMASequencer.hh c81401cf5cc2 > src/mem/ruby/system/RubyPort.hh c81401cf5cc2 > src/mem/ruby/system/RubySystem.hh c81401cf5cc2 > src/mem/ruby/system/Sequencer.hh c81401cf5cc2 > src/mem/ruby/system/Sequencer.cc c81401cf5cc2 > src/mem/simple_mem.hh c81401cf5cc2 > src/mem/snoop_filter.hh c81401cf5cc2 > src/mem/xbar.hh c81401cf5cc2 > src/sim/clock_domain.hh c81401cf5cc2 > src/sim/dvfs_handler.hh c81401cf5cc2 > src/sim/eventq.hh c81401cf5cc2 > src/sim/eventq.cc c81401cf5cc2 > src/sim/fd_entry.hh c81401cf5cc2 > src/sim/process.hh c81401cf5cc2 > src/sim/root.hh c81401cf5cc2 > src/sim/serialize.cc c81401cf5cc2 > src/mem/cache/tags/base_set_assoc.hh c81401cf5cc2 > src/mem/cache/tags/fa_lru.hh c81401cf5cc2 > src/mem/cache/prefetch/stride.hh c81401cf5cc2 > src/dev/sparc/mm_disk.hh c81401cf5cc2 > src/dev/tcp_iface.hh c81401cf5cc2 > src/dev/uart8250.hh c81401cf5cc2 > src/dev/virtio/base.hh c81401cf5cc2 > src/dev/virtio/fs9p.hh c81401cf5cc2 > src/dev/x86/cmos.hh c81401cf5cc2 > src/dev/x86/i8042.hh c81401cf5cc2 > src/dev/x86/i82094aa.hh c81401cf5cc2 > src/dev/x86/i8237.hh c81401cf5cc2 > src/dev/x86/i8254.hh c81401cf5cc2 > src/dev/x86/i8259.hh c81401cf5cc2 > src/dev/x86/speaker.hh c81401cf5cc2 > src/kern/kernel_stats.hh c81401cf5cc2 > src/mem/cache/cache.hh c81401cf5cc2 > src/mem/cache/mshr_queue.hh c81401cf5cc2 > src/dev/arm/energy_ctrl.hh c81401cf5cc2 > src/dev/arm/flash_device.hh c81401cf5cc2 > src/dev/arm/generic_timer.hh c81401cf5cc2 > src/dev/arm/gic_pl390.hh c81401cf5cc2 > src/dev/arm/gpu_nomali.hh c81401cf5cc2 > src/dev/arm/hdlcd.hh c81401cf5cc2 > src/dev/arm/kmi.hh c81401cf5cc2 > src/dev/arm/pl011.hh c81401cf5cc2 > src/dev/arm/pl111.hh c81401cf5cc2 > src/dev/arm/rtc_pl031.hh c81401cf5cc2 > src/dev/arm/rv_ctrl.hh c81401cf5cc2 > src/dev/arm/timer_cpulocal.hh c81401cf5cc2 > src/dev/arm/timer_sp804.hh c81401cf5cc2 > src/dev/arm/ufs_device.hh c81401cf5cc2 > src/dev/arm/vgic.hh c81401cf5cc2 > src/dev/copy_engine.hh c81401cf5cc2 > src/dev/copy_engine_defs.hh c81401cf5cc2 > src/dev/disk_image.hh c81401cf5cc2 > src/dev/dma_device.hh c81401cf5cc2 > src/dev/etherlink.hh c81401cf5cc2 > src/dev/ethertap.hh c81401cf5cc2 > src/dev/i2cbus.hh c81401cf5cc2 > src/dev/i8254xGBe.hh c81401cf5cc2 > src/dev/i8254xGBe_defs.hh c81401cf5cc2 > src/dev/ide_ctrl.hh c81401cf5cc2 > src/dev/ide_disk.hh c81401cf5cc2 > src/dev/mips/malta.hh c81401cf5cc2 > src/dev/mips/malta_cchip.hh c81401cf5cc2 > src/dev/mips/malta_io.hh c81401cf5cc2 > src/dev/mips/malta_pchip.hh c81401cf5cc2 > src/dev/multi_etherlink.hh c81401cf5cc2 > src/dev/multi_iface.hh c81401cf5cc2 > src/dev/ns_gige.hh c81401cf5cc2 > src/dev/pcidev.hh c81401cf5cc2 > src/dev/pixelpump.hh c81401cf5cc2 > src/dev/sinic.hh c81401cf5cc2 > src/dev/sparc/dtod.hh c81401cf5cc2 > src/dev/sparc/iob.hh c81401cf5cc2 > src/base/framebuffer.hh c81401cf5cc2 > src/base/hashmap.hh c81401cf5cc2 > src/base/inifile.hh c81401cf5cc2 > src/base/pollevent.hh c81401cf5cc2 > src/base/random.hh c81401cf5cc2 > src/base/trace.hh c81401cf5cc2 > src/base/vnc/vncserver.hh c81401cf5cc2 > src/cpu/base.hh c81401cf5cc2 > src/cpu/checker/cpu.hh c81401cf5cc2 > src/cpu/decode_cache.hh c81401cf5cc2 > src/cpu/inst_pb_trace.hh c81401cf5cc2 > src/cpu/kvm/base.hh c81401cf5cc2 > src/cpu/kvm/x86_cpu.hh c81401cf5cc2 > src/cpu/minor/cpu.hh c81401cf5cc2 > src/cpu/minor/pipeline.hh c81401cf5cc2 > src/cpu/o3/cpu.hh c81401cf5cc2 > src/cpu/o3/lsq_unit.hh c81401cf5cc2 > src/cpu/o3/mem_dep_unit.hh c81401cf5cc2 > src/cpu/o3/thread_state.hh c81401cf5cc2 > src/cpu/pred/bpred_unit.hh c81401cf5cc2 > src/cpu/simple/atomic.hh c81401cf5cc2 > src/cpu/simple/base.hh c81401cf5cc2 > src/cpu/simple/exec_context.hh c81401cf5cc2 > src/cpu/simple/probes/simpoint.hh c81401cf5cc2 > src/cpu/simple/timing.hh c81401cf5cc2 > src/cpu/simple_thread.hh c81401cf5cc2 > src/cpu/testers/rubytest/CheckTable.hh c81401cf5cc2 > src/cpu/testers/rubytest/CheckTable.cc c81401cf5cc2 > src/arch/alpha/kernel_stats.hh c81401cf5cc2 > src/arch/alpha/pagetable.hh c81401cf5cc2 > src/arch/alpha/process.hh c81401cf5cc2 > src/arch/alpha/system.hh c81401cf5cc2 > src/arch/alpha/tlb.hh c81401cf5cc2 > src/arch/arm/isa_device.hh c81401cf5cc2 > src/arch/arm/kvm/armv8_cpu.hh c81401cf5cc2 > src/arch/arm/kvm/base_cpu.hh c81401cf5cc2 > src/arch/arm/kvm/gic.hh c81401cf5cc2 > src/arch/arm/pagetable.hh c81401cf5cc2 > src/arch/arm/pmu.hh c81401cf5cc2 > src/arch/arm/table_walker.hh c81401cf5cc2 > src/arch/arm/tlb.hh c81401cf5cc2 > src/arch/arm/types.hh c81401cf5cc2 > src/arch/generic/types.hh c81401cf5cc2 > src/arch/mips/interrupts.hh c81401cf5cc2 > src/arch/mips/tlb.hh c81401cf5cc2 > src/arch/power/tlb.hh c81401cf5cc2 > src/arch/power/types.hh c81401cf5cc2 > src/arch/sparc/interrupts.hh c81401cf5cc2 > src/arch/sparc/isa.hh c81401cf5cc2 > src/arch/sparc/system.hh c81401cf5cc2 > src/arch/sparc/tlb.hh c81401cf5cc2 > src/arch/x86/decoder.hh c81401cf5cc2 > src/arch/x86/interrupts.hh c81401cf5cc2 > src/arch/x86/isa.hh c81401cf5cc2 > src/arch/x86/pagetable.hh c81401cf5cc2 > src/arch/x86/regs/msr.hh c81401cf5cc2 > src/arch/x86/tlb.hh c81401cf5cc2 > src/arch/x86/types.hh c81401cf5cc2 > src/arch/x86/utility.hh c81401cf5cc2 > src/base/compiler.hh c81401cf5cc2 > src/base/cp_annotate.hh c81401cf5cc2 > src/arch/alpha/isa.hh c81401cf5cc2 > src/cpu/testers/traffic_gen/traffic_gen.hh c81401cf5cc2 > src/cpu/thread_state.hh c81401cf5cc2 > src/dev/alpha/backdoor.hh c81401cf5cc2 > src/dev/alpha/tsunami.hh c81401cf5cc2 > src/dev/alpha/tsunami_cchip.hh c81401cf5cc2 > src/dev/alpha/tsunami_io.hh c81401cf5cc2 > src/dev/alpha/tsunami_pchip.hh c81401cf5cc2 > > Diff: http://reviews.gem5.org/r/3147/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
