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src/mem/packet_queue.cc (lines 138 - 172) <http://reviews.gem5.org/r/3153/#comment6220> This looks complicated and I think we can simplify it. How about the following? This should include everything from line 138 to 172. it = list.end(); it--; while (it != list.begin()) { if (it->time <= pkt->time()) || (force_order && it.address == pkt->address)) insert(); break; } - Nilay Vaish On Oct. 13, 2015, 3:36 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3153/ > ----------------------------------------------------------- > > (Updated Oct. 13, 2015, 3:36 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11172:c6a961a268fd > --------------------------- > mem: Order packet queue only on matching addresses > > Instead of conservatively enforcing order for all packets, which may > negatively impact the simulated-system performance, this patch updates > the packet queue such that it only applies the restriction if there > are already packets with the same address in the queue. > > The basic need for the order enforcement is due to coherency > interactions where requests/responses to the same cache line must not > over-take each other. We rely on the fact that any packet that needs > order enforcement will have a block-aligned address. Thus, there is no > need for the queue to know about the cacheline size. > > > Diffs > ----- > > src/mem/packet_queue.hh 44b5c183c3cd > src/mem/packet_queue.cc 44b5c183c3cd > > Diff: http://reviews.gem5.org/r/3153/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
