Thank you..! On Mon, Oct 19, 2015 at 2:56 PM, Virendra Kumar Pathak < [email protected]> wrote:
> Hi Sruthi, > > I am not sure if gem5-dev is the correct place for asking question > (gem5-users ?). > > You can look configs/common/O3_ARM_v7a.py, where L2 is defined as: > class O3_ARM_v7aL2(Cache): > hit_latency = 12 > response_latency = 12 > ..... > ..... > > And config/common/CacheConfig.py, where L2 is added with memory bars > if options.l2cache: > system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, > size=options.l2_size, > assoc=options.l2_assoc) > system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) > system.l2.cpu_side = system.tol2bus.master > system.l2.mem_side = system.membus.slave > > Thanks. > > -- > with regards, > Virendra Kumar Pathak > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
