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Page faults don't actually happen when they're detected by the TLB, they happen when the page fault is invoked later. That may never happen if an instruction is running speculatively, or potentially if a translation is done for some reason other than instruction execution. Side effects like the one you're adding should happen during the invoke, not when the fault is detected. - Gabe Black On Oct. 26, 2015, 5:26 p.m., Swapnil Haria wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3167/ > ----------------------------------------------------------- > > (Updated Oct. 26, 2015, 5:26 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11179:f5cb3abbb62b > --------------------------- > Invalidating TLB entry on page fault in x86 > > As per the x86 architecture specification, matching TLB entries need to be > invalidated on a page fault. For instance, after a page fault due to > inadequate > protection bits on a TLB hit, the TLB entry needs to be invalidated. This > behavior is clearly specified in the x86 architecture manuals from both AMD > and > Intel. This invalidation is missing currently in gem5, due to which linux > kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by > a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which > removes a tlb flush on updating page table entries in x86. > > Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS > mode, > due to repeated page faults (~300000 before the first print statement in a > bash > file). Ensured that page fault rate drops drastically and observed reduction > in > boot time from order of hours to minutes for linux kernel v3.8 and v3.11 > > > Diffs > ----- > > src/arch/x86/tlb.hh 741b3059946e > src/arch/x86/tlb.cc 741b3059946e > > Diff: http://reviews.gem5.org/r/3167/diff/ > > > Testing > ------- > > > Thanks, > > Swapnil Haria > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
