Is it so ? On Fri, Oct 30, 2015 at 7:13 PM, P Pinky <[email protected]> wrote:
> Hi all > Why do we have tablewalker cache ? > > From the description " X86: *Add* *L1* *caches* for the *TLB* *walkers*. > Small *L1* *caches* are connected to the *TLB* *walkers* when *caches *are > used. This allows them to participate in the coherence protocol properly." > > Does this means , by using pagewalker cache TLBs can communicate with > caches in coherence protocol ? > > Thanks in advance > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
