[gem5-dev] changeset in gem5: cpu: Fix base FP and CC register index in o3 ...

[Nathanael Premillieu]

changeset 9bc552f9e4b0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9bc552f9e4b0
description:
        cpu: Fix base FP and CC register index in o3 insertThread()

        Note that the method is not used, and could possibly be deleted.

diffstat:

 src/cpu/o3/cpu.cc |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (25 lines):

diff -r a7a718faaf56 -r 9bc552f9e4b0 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sun Nov 22 05:10:18 2015 -0500
+++ b/src/cpu/o3/cpu.cc Sun Nov 22 05:10:19 2015 -0500
@@ -790,8 +790,8 @@
     }
 
     //Bind Float Regs to Rename Map
-    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
+    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
+    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
         PhysRegIndex phys_reg = freeList.getFloatReg();
 
         renameMap[tid].setEntry(freg,phys_reg);
@@ -799,8 +799,8 @@
     }
 
     //Bind condition-code Regs to Rename Map
-    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
-    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
+    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
+    for (int creg = TheISA::CC_Reg_Base;
          creg < max_reg; creg++) {
         PhysRegIndex phys_reg = freeList.getCCReg();
 
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