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(Updated Nov. 24, 2015, 2:51 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11222:69ed6a935de7 --------------------------- dev, arm: Add gem5 extensions to support more than 8 cores Previous ARM-based simulations were limited to 8 cores due to limitations in GICv2 and earlier. This changeset adds a set of gem5-specific extensions that enable support for up to 256 cores. When the gem5 extensions are enabled, the GIC uses CPU IDs instead of a CPU bitmask in the GIC's register interface. To OS can enable the extensions by setting bit 0x200 in ICDICTR. This changeset is based on previous work by Matt Evans. Diffs (updated) ----- src/dev/arm/gic_pl390.hh c0ea80fed78f src/dev/arm/gic_pl390.cc c0ea80fed78f util/cpt_upgraders/arm-gem5-gic-ext.py PRE-CREATION Diff: http://reviews.gem5.org/r/3232/diff/ Testing ------- Thanks, Andreas Sandberg _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
