changeset 18e411ee6c04 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=18e411ee6c04
description:
dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the
class name) to the TsunamiPChip. If someone decides to implement PCI
for Malta, they should make sure to share code with the Tsunami
implementation if they are similar.
diffstat:
src/dev/mips/Malta.py | 6 -
src/dev/mips/SConscript | 2 +-
src/dev/mips/malta.cc | 1 -
src/dev/mips/malta.hh | 7 -
src/dev/mips/malta_pchip.cc | 337 --------------------------------------------
src/dev/mips/malta_pchip.hh | 95 ------------
6 files changed, 1 insertions(+), 447 deletions(-)
diffs (truncated from 507 to 300 lines):
diff -r 135c16fa409d -r 18e411ee6c04 src/dev/mips/Malta.py
--- a/src/dev/mips/Malta.py Wed Dec 02 09:58:24 2015 -0500
+++ b/src/dev/mips/Malta.py Thu Dec 03 23:09:34 2015 +0000
@@ -31,7 +31,6 @@
from BadDevice import BadDevice
from Device import BasicPioDevice
-from Pci import PciConfigAll
from Platform import Platform
from Uart import Uart8250
@@ -50,11 +49,6 @@
malta = Param.Malta(Parent.any, "Malta")
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-class MaltaPChip(BasicPioDevice):
- type = 'MaltaPChip'
- cxx_header = "dev/mips/malta_pchip.hh"
- malta = Param.Malta(Parent.any, "Malta")
-
class Malta(Platform):
type = 'Malta'
cxx_header = "dev/mips/malta.hh"
diff -r 135c16fa409d -r 18e411ee6c04 src/dev/mips/SConscript
--- a/src/dev/mips/SConscript Wed Dec 02 09:58:24 2015 -0500
+++ b/src/dev/mips/SConscript Thu Dec 03 23:09:34 2015 +0000
@@ -39,4 +39,4 @@
Source('malta.cc')
Source('malta_cchip.cc')
Source('malta_io.cc')
- Source('malta_pchip.cc')
+
diff -r 135c16fa409d -r 18e411ee6c04 src/dev/mips/malta.cc
--- a/src/dev/mips/malta.cc Wed Dec 02 09:58:24 2015 -0500
+++ b/src/dev/mips/malta.cc Thu Dec 03 23:09:34 2015 +0000
@@ -43,7 +43,6 @@
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
-#include "dev/mips/malta_pchip.hh"
#include "dev/terminal.hh"
#include "params/Malta.hh"
#include "sim/system.hh"
diff -r 135c16fa409d -r 18e411ee6c04 src/dev/mips/malta.hh
--- a/src/dev/mips/malta.hh Wed Dec 02 09:58:24 2015 -0500
+++ b/src/dev/mips/malta.hh Thu Dec 03 23:09:34 2015 +0000
@@ -43,7 +43,6 @@
class IdeController;
class MaltaCChip;
-class MaltaPChip;
class MaltaIO;
class System;
@@ -72,12 +71,6 @@
*/
MaltaCChip *cchip;
- /** Pointer to the Malta PChip.
- * The pchip is the interface to the PCI bus, in our case
- * it does not have to do much.
- */
- MaltaPChip *pchip;
-
int intr_sum_type[Malta::Max_CPUs];
int ipi_pending[Malta::Max_CPUs];
diff -r 135c16fa409d -r 18e411ee6c04 src/dev/mips/malta_pchip.cc
--- a/src/dev/mips/malta_pchip.cc Wed Dec 02 09:58:24 2015 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,337 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Andrew Schultz
- */
-
-/** @file
- * Malta PChip (pci)
- */
-
-#include <deque>
-#include <string>
-#include <vector>
-
-#include "base/trace.hh"
-#include "config/the_isa.hh"
-#include "debug/Malta.hh"
-#include "dev/mips/malta.hh"
-#include "dev/mips/malta_pchip.hh"
-#include "dev/mips/maltareg.h"
-#include "mem/packet.hh"
-#include "mem/packet_access.hh"
-#include "sim/system.hh"
-
-using namespace std;
-using namespace TheISA;
-
-MaltaPChip::MaltaPChip(const Params *p)
- : BasicPioDevice(p, 0x1000)
-{
- for (int i = 0; i < 4; i++) {
- wsba[i] = 0;
- wsm[i] = 0;
- tba[i] = 0;
- }
-
- // initialize pchip control register
- pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
-
- //Set back pointer in malta
- p->malta->pchip = this;
-}
-
-Tick
-MaltaPChip::read(PacketPtr pkt)
-{
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
-
- Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
- assert(pkt->getSize() == sizeof(uint64_t));
-
-
- DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
-
- switch(daddr) {
- case TSDEV_PC_WSBA0:
- pkt->set(wsba[0]);
- break;
- case TSDEV_PC_WSBA1:
- pkt->set(wsba[1]);
- break;
- case TSDEV_PC_WSBA2:
- pkt->set(wsba[2]);
- break;
- case TSDEV_PC_WSBA3:
- pkt->set(wsba[3]);
- break;
- case TSDEV_PC_WSM0:
- pkt->set(wsm[0]);
- break;
- case TSDEV_PC_WSM1:
- pkt->set(wsm[1]);
- break;
- case TSDEV_PC_WSM2:
- pkt->set(wsm[2]);
- break;
- case TSDEV_PC_WSM3:
- pkt->set(wsm[3]);
- break;
- case TSDEV_PC_TBA0:
- pkt->set(tba[0]);
- break;
- case TSDEV_PC_TBA1:
- pkt->set(tba[1]);
- break;
- case TSDEV_PC_TBA2:
- pkt->set(tba[2]);
- break;
- case TSDEV_PC_TBA3:
- pkt->set(tba[3]);
- break;
- case TSDEV_PC_PCTL:
- pkt->set(pctl);
- break;
- case TSDEV_PC_PLAT:
- panic("PC_PLAT not implemented\n");
- case TSDEV_PC_RES:
- panic("PC_RES not implemented\n");
- case TSDEV_PC_PERROR:
- pkt->set((uint64_t)0x00);
- break;
- case TSDEV_PC_PERRMASK:
- pkt->set((uint64_t)0x00);
- break;
- case TSDEV_PC_PERRSET:
- panic("PC_PERRSET not implemented\n");
- case TSDEV_PC_TLBIV:
- panic("PC_TLBIV not implemented\n");
- case TSDEV_PC_TLBIA:
- pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
- break;
- case TSDEV_PC_PMONCTL:
- panic("PC_PMONCTL not implemented\n");
- case TSDEV_PC_PMONCNT:
- panic("PC_PMONCTN not implemented\n");
- default:
- panic("Default in PChip Read reached reading 0x%x\n", daddr);
- }
- pkt->makeAtomicResponse();
- return pioDelay;
-
-}
-
-Tick
-MaltaPChip::write(PacketPtr pkt)
-{
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
-
- assert(pkt->getSize() == sizeof(uint64_t));
-
- DPRINTF(Malta, "write - va=%#x size=%d \n", pkt->getAddr(),
pkt->getSize());
-
- switch(daddr) {
- case TSDEV_PC_WSBA0:
- wsba[0] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSBA1:
- wsba[1] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSBA2:
- wsba[2] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSBA3:
- wsba[3] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSM0:
- wsm[0] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSM1:
- wsm[1] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSM2:
- wsm[2] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_WSM3:
- wsm[3] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_TBA0:
- tba[0] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_TBA1:
- tba[1] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_TBA2:
- tba[2] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_TBA3:
- tba[3] = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_PCTL:
- pctl = pkt->get<uint64_t>();
- break;
- case TSDEV_PC_PLAT:
- panic("PC_PLAT not implemented\n");
- case TSDEV_PC_RES:
- panic("PC_RES not implemented\n");
- case TSDEV_PC_PERROR:
- break;
- case TSDEV_PC_PERRMASK:
- panic("PC_PERRMASK not implemented\n");
- case TSDEV_PC_PERRSET:
- panic("PC_PERRSET not implemented\n");
- case TSDEV_PC_TLBIV:
- panic("PC_TLBIV not implemented\n");
- case TSDEV_PC_TLBIA:
- break; // value ignored, supposted to invalidate SG TLB
- case TSDEV_PC_PMONCTL:
- panic("PC_PMONCTL not implemented\n");
- case TSDEV_PC_PMONCNT:
- panic("PC_PMONCTN not implemented\n");
- default:
- panic("Default in PChip write reached reading 0x%x\n", daddr);
-
- } // uint64_t
-
- pkt->makeAtomicResponse();
- return pioDelay;
-}
-
-#define DMA_ADDR_MASK ULL(0x3ffffffff)
-
-Addr
-MaltaPChip::translatePciToDma(Addr busAddr)
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
