changeset a2af58a06c4e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a2af58a06c4e
description:
dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
diffstat:
configs/common/FSConfig.py | 4 -
src/dev/Pci.py | 19 +-
src/dev/SConscript | 2 -
src/dev/alpha/Tsunami.py | 17 +-
src/dev/alpha/tsunami.cc | 25 ---
src/dev/alpha/tsunami.hh | 39 +----
src/dev/alpha/tsunami_pchip.cc | 59 +++---
src/dev/alpha/tsunami_pchip.hh | 32 ++-
src/dev/arm/RealView.py | 30 +-
src/dev/arm/realview.cc | 49 +-----
src/dev/arm/realview.hh | 44 +----
src/dev/pci/PciHost.py | 64 +++++++
src/dev/pci/SConscript | 48 +++++
src/dev/pci/host.cc | 228 ++++++++++++++++++++++++++++
src/dev/pci/host.hh | 330 +++++++++++++++++++++++++++++++++++++++++
src/dev/pci/types.hh | 74 +++++++++
src/dev/pciconfigall.cc | 94 -----------
src/dev/pciconfigall.hh | 83 ----------
src/dev/pcidev.cc | 77 ++-------
src/dev/pcidev.hh | 87 ++--------
src/dev/platform.cc | 22 --
src/dev/platform.hh | 30 ++-
src/dev/x86/Pc.py | 13 +-
src/dev/x86/SouthBridge.py | 1 -
src/dev/x86/pc.cc | 27 ---
src/dev/x86/pc.hh | 41 +----
26 files changed, 901 insertions(+), 638 deletions(-)
diffs (truncated from 2144 to 300 lines):
diff -r f876d08c7b21 -r a2af58a06c4e configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Fri Dec 04 17:54:03 2015 -0600
+++ b/configs/common/FSConfig.py Sat Dec 05 00:11:24 2015 +0000
@@ -94,10 +94,8 @@
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.master
- self.tsunami.ide.config = self.iobus.master
self.tsunami.ethernet.pio = self.iobus.master
- self.tsunami.ethernet.config = self.iobus.master
if ruby:
# Store the dma devices for later connection to dma ruby ports.
@@ -396,10 +394,8 @@
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.master
- self.malta.ide.config = self.iobus.master
self.malta.ide.dma = self.iobus.slave
self.malta.ethernet.pio = self.iobus.master
- self.malta.ethernet.config = self.iobus.master
self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/Pci.py
--- a/src/dev/Pci.py Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/Pci.py Sat Dec 05 00:11:24 2015 +0000
@@ -41,29 +41,20 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice, DmaDevice, PioDevice
-
-class PciConfigAll(BasicPioDevice):
- type = 'PciConfigAll'
- cxx_header = "dev/pciconfigall.hh"
- platform = Param.Platform(Parent.any, "Platform this device is part of.")
- bus = Param.UInt8(0x00, "PCI bus to act as config space for")
- size = Param.MemorySize32('16MB', "Size of config space")
-
- pio_latency = '30ns'
- pio_addr = 0 # will be overridden by platform-based calculation
-
+from Device import DmaDevice
+from PciHost import PciHost
class PciDevice(DmaDevice):
type = 'PciDevice'
cxx_class = 'PciDevice'
cxx_header = "dev/pcidev.hh"
abstract = True
- platform = Param.Platform(Parent.any, "Platform this device is part of.")
- config = SlavePort("PCI configuration space port")
+
+ host = Param.PciHost(Parent.any, "PCI host")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
+
pio_latency = Param.Latency('30ns', "Programmed IO latency")
config_latency = Param.Latency('20ns', "Config read or write latency")
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/SConscript
--- a/src/dev/SConscript Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/SConscript Sat Dec 05 00:11:24 2015 +0000
@@ -73,7 +73,6 @@
Source('intel_8254_timer.cc')
Source('mc146818.cc')
Source('ns_gige.cc')
-Source('pciconfigall.cc')
Source('pcidev.cc')
Source('pixelpump.cc')
Source('pktfifo.cc')
@@ -105,7 +104,6 @@
DebugFlag('Intel8254Timer')
DebugFlag('MC146818')
DebugFlag('PCIDEV')
-DebugFlag('PciConfigAll')
DebugFlag('SimpleDisk')
DebugFlag('SimpleDiskData')
DebugFlag('Terminal')
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/alpha/Tsunami.py
--- a/src/dev/alpha/Tsunami.py Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/alpha/Tsunami.py Sat Dec 05 00:11:24 2015 +0000
@@ -31,7 +31,7 @@
from BadDevice import BadDevice
from AlphaBackdoor import AlphaBackdoor
from Device import BasicPioDevice, IsaFake, BadAddr
-from Pci import PciConfigAll
+from PciHost import GenericPciHost
from Platform import Platform
from Uart import Uart8250
@@ -50,9 +50,19 @@
tsunami = Param.Tsunami(Parent.any, "Tsunami")
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-class TsunamiPChip(BasicPioDevice):
+class TsunamiPChip(GenericPciHost):
type = 'TsunamiPChip'
cxx_header = "dev/alpha/tsunami_pchip.hh"
+
+ conf_base = 0x801fe000000
+ conf_size = "16MB"
+
+ pci_pio_base = 0x801fc000000
+ pci_mem_base = 0x80000000000
+
+ pio_addr = Param.Addr("Device Address")
+ pio_latency = Param.Latency('100ns', "Programmed IO latency")
+
tsunami = Param.Tsunami(Parent.any, "Tsunami")
class Tsunami(Platform):
@@ -62,7 +72,6 @@
cchip = TsunamiCChip(pio_addr=0x801a0000000)
pchip = TsunamiPChip(pio_addr=0x80180000000)
- pciconfig = PciConfigAll()
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
@@ -99,8 +108,6 @@
def attachIO(self, bus):
self.cchip.pio = bus.master
self.pchip.pio = bus.master
- self.pciconfig.pio = bus.default
- bus.use_default_range = True
self.fake_sm_chip.pio = bus.master
self.fake_uart1.pio = bus.master
self.fake_uart2.pio = bus.master
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/alpha/tsunami.cc
--- a/src/dev/alpha/tsunami.cc Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/alpha/tsunami.cc Sat Dec 05 00:11:24 2015 +0000
@@ -88,31 +88,6 @@
cchip->clearDRIR(line);
}
-Addr
-Tsunami::pciToDma(Addr pciAddr) const
-{
- return pchip->translatePciToDma(pciAddr);
-}
-
-
-Addr
-Tsunami::calcPciConfigAddr(int bus, int dev, int func)
-{
- return pchip->calcConfigAddr(bus, dev, func);
-}
-
-Addr
-Tsunami::calcPciIOAddr(Addr addr)
-{
- return pchip->calcIOAddr(addr);
-}
-
-Addr
-Tsunami::calcPciMemAddr(Addr addr)
-{
- return pchip->calcMemAddr(addr);
-}
-
void
Tsunami::serialize(CheckpointOut &cp) const
{
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/alpha/tsunami.hh
--- a/src/dev/alpha/tsunami.hh Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/alpha/tsunami.hh Sat Dec 05 00:11:24 2015 +0000
@@ -86,46 +86,15 @@
typedef TsunamiParams Params;
Tsunami(const Params *p);
- /**
- * Cause the cpu to post a serial interrupt to the CPU.
- */
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ public: // Public Platform interfaces
void postConsoleInt() override;
-
- /**
- * Clear a posted CPU interrupt (id=55)
- */
void clearConsoleInt() override;
- /**
- * Cause the chipset to post a cpi interrupt to the CPU.
- */
void postPciInt(int line) override;
-
- /**
- * Clear a posted PCI->CPU interrupt
- */
void clearPciInt(int line) override;
-
-
- Addr pciToDma(Addr pciAddr) const override;
-
- /**
- * Calculate the configuration address given a bus/dev/func.
- */
- Addr calcPciConfigAddr(int bus, int dev, int func) override;
-
- /**
- * Calculate the address for an IO location on the PCI bus.
- */
- Addr calcPciIOAddr(Addr addr) override;
-
- /**
- * Calculate the address for a memory location on the PCI bus.
- */
- Addr calcPciMemAddr(Addr addr) override;
-
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_TSUNAMI_HH__
diff -r f876d08c7b21 -r a2af58a06c4e src/dev/alpha/tsunami_pchip.cc
--- a/src/dev/alpha/tsunami_pchip.cc Fri Dec 04 17:54:03 2015 -0600
+++ b/src/dev/alpha/tsunami_pchip.cc Sat Dec 05 00:11:24 2015 +0000
@@ -32,6 +32,7 @@
/** @file
* Tsunami PChip (pci)
*/
+#include "dev/alpha/tsunami_pchip.hh"
#include <deque>
#include <string>
@@ -41,8 +42,9 @@
#include "config/the_isa.hh"
#include "debug/Tsunami.hh"
#include "dev/alpha/tsunami.hh"
-#include "dev/alpha/tsunami_pchip.hh"
+#include "dev/alpha/tsunami_cchip.hh"
#include "dev/alpha/tsunamireg.h"
+#include "dev/pcidev.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"
@@ -52,7 +54,9 @@
using namespace TheISA;
TsunamiPChip::TsunamiPChip(const Params *p)
- : BasicPioDevice(p, 0x1000)
+ : GenericPciHost(p),
+ pioRange(RangeSize(p->pio_addr, 0x1000)),
+ pioDelay(p->pio_latency)
{
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
@@ -70,9 +74,12 @@
Tick
TsunamiPChip::read(PacketPtr pkt)
{
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+ // We only need to handle our own configuration registers, pass
+ // unknown addresses to the generic code.
+ if (!pioRange.contains(pkt->getAddr()))
+ return GenericPciHost::read(pkt);
- Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
+ Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;;
assert(pkt->getSize() == sizeof(uint64_t));
@@ -142,6 +149,7 @@
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
}
+
pkt->makeAtomicResponse();
return pioDelay;
@@ -150,8 +158,12 @@
Tick
TsunamiPChip::write(PacketPtr pkt)
{
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
+ // We only need to handle our own configuration registers, pass
+ // unknown addresses to the generic code.
+ if (!pioRange.contains(pkt->getAddr()))
+ return GenericPciHost::write(pkt);
+
+ Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;
assert(pkt->getSize() == sizeof(uint64_t));
@@ -224,10 +236,21 @@
return pioDelay;
}
+
+AddrRangeList
+TsunamiPChip::getAddrRanges() const
+{
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