changeset 93d2a1526103 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=93d2a1526103
description:
probe: Add probe in Fetch, IEW, Rename and Commit
This patch adds probe points in Fetch, IEW, Rename and Commit stages as
follows.
A probe point is added in the Fetch stage for probing when a fetch
request is
sent. Notify is fired on the probe point when a request is sent
succesfully in
the first attempt as well as on a retry attempt.
Probe points are added in the IEW stage when an instruction begins to
execute
and when execution is complete. This points can be used for monitoring
the
execution time of an instruction.
Probe points are added in the Rename stage to probe renaming of source
and
destination registers and when there is squashing. These probe points
can be
used to track register dependencies and remove when there is squashing.
A probe point for squashing is added in Commit to probe squashed
instructions.
diffstat:
src/cpu/o3/commit.hh | 2 ++
src/cpu/o3/commit_impl.hh | 3 +++
src/cpu/o3/cpu.cc | 1 +
src/cpu/o3/fetch.hh | 2 ++
src/cpu/o3/fetch_impl.hh | 9 +++++++++
src/cpu/o3/iew.hh | 4 ++++
src/cpu/o3/iew_impl.hh | 19 +++++++++++++++++++
src/cpu/o3/rename.hh | 15 +++++++++++++++
src/cpu/o3/rename_impl.hh | 19 ++++++++++++++++++-
9 files changed, 73 insertions(+), 1 deletions(-)
diffs (231 lines):
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/commit.hh Mon Dec 07 16:42:15 2015 -0600
@@ -154,6 +154,8 @@
/** Probe Points. */
ProbePointArg<DynInstPtr> *ppCommit;
ProbePointArg<DynInstPtr> *ppCommitStall;
+ /** To probe when an instruction is squashed */
+ ProbePointArg<DynInstPtr> *ppSquash;
public:
/** Construct a DefaultCommit with the given parameters. */
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/commit_impl.hh Mon Dec 07 16:42:15 2015 -0600
@@ -173,6 +173,7 @@
{
ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"CommitStall");
+ ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
}
template <class Impl>
@@ -1010,6 +1011,8 @@
rob->retireHead(commit_thread);
++commitSquashedInsts;
+ // Notify potential listeners that this instruction is squashed
+ ppSquash->notify(head_inst);
// Record that the number of ROB entries has changed.
changedROBNumEntries[tid] = true;
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/cpu.cc Mon Dec 07 16:42:15 2015 -0600
@@ -416,6 +416,7 @@
ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr>
>(getProbeManager(), "DataAccessComplete");
fetch.regProbePoints();
+ rename.regProbePoints();
iew.regProbePoints();
commit.regProbePoints();
}
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/fetch.hh Mon Dec 07 16:42:15 2015 -0600
@@ -197,6 +197,8 @@
/** Probe points. */
ProbePointArg<DynInstPtr> *ppFetch;
+ /** To probe when a fetch request is successfully sent. */
+ ProbePointArg<RequestPtr> *ppFetchRequestSent;
public:
/** DefaultFetch constructor. */
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/fetch_impl.hh Mon Dec 07 16:42:15 2015 -0600
@@ -171,6 +171,9 @@
DefaultFetch<Impl>::regProbePoints()
{
ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch");
+ ppFetchRequestSent = new ProbePointArg<RequestPtr>(cpu->getProbeManager(),
+ "FetchRequest");
+
}
template <class Impl>
@@ -695,6 +698,9 @@
"response.\n", tid);
lastIcacheStall[tid] = curTick();
fetchStatus[tid] = IcacheWaitResponse;
+ // Notify Fetch Request probe when a packet containing a fetch
+ // request is successfully sent
+ ppFetchRequestSent->notify(mem_req);
}
} else {
// Don't send an instruction to decode if we can't handle it.
@@ -1422,6 +1428,9 @@
if (cpu->getInstPort().sendTimingReq(retryPkt)) {
fetchStatus[retryTid] = IcacheWaitResponse;
+ // Notify Fetch Request probe when a retryPkt is successfully sent.
+ // Note that notify must be called before retryPkt is set to NULL.
+ ppFetchRequestSent->notify(retryPkt->req);
retryPkt = NULL;
retryTid = InvalidThreadID;
cacheBlocked = false;
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/iew.hh Mon Dec 07 16:42:15 2015 -0600
@@ -126,6 +126,10 @@
/** Probe points. */
ProbePointArg<DynInstPtr> *ppMispredict;
ProbePointArg<DynInstPtr> *ppDispatch;
+ /** To probe when instruction execution begins. */
+ ProbePointArg<DynInstPtr> *ppExecute;
+ /** To probe when instruction execution is complete. */
+ ProbePointArg<DynInstPtr> *ppToCommit;
public:
/** Constructs a DefaultIEW with the given parameters. */
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/iew_impl.hh Mon Dec 07 16:42:15 2015 -0600
@@ -125,6 +125,18 @@
{
ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"Dispatch");
ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
"Mispredict");
+ /**
+ * Probe point with dynamic instruction as the argument used to probe when
+ * an instruction starts to execute.
+ */
+ ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
+ "Execute");
+ /**
+ * Probe point with dynamic instruction as the argument used to probe when
+ * an instruction execution completes and it is marked ready to commit.
+ */
+ ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
+ "ToCommit");
}
template <class Impl>
@@ -1190,6 +1202,10 @@
DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
inst->pcState(), inst->threadNumber,inst->seqNum);
+ // Notify potential listeners that this instruction has started
+ // executing
+ ppExecute->notify(inst);
+
// Check if the instruction is squashed; if so then skip it
if (inst->isSquashed()) {
DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
@@ -1402,6 +1418,9 @@
inst->seqNum, inst->pcState());
iewInstsToCommit[tid]++;
+ // Notify potential listeners that execution is complete for this
+ // instruction.
+ ppToCommit->notify(inst);
// Some instructions will be sent to commit without having
// executed because they need commit to handle them.
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/rename.hh
--- a/src/cpu/o3/rename.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/rename.hh Mon Dec 07 16:42:15 2015 -0600
@@ -45,10 +45,12 @@
#define __CPU_O3_RENAME_HH__
#include <list>
+#include <utility>
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/timebuf.hh"
+#include "sim/probe/probe.hh"
struct DerivO3CPUParams;
@@ -119,6 +121,16 @@
/** Per-thread status. */
ThreadStatus renameStatus[Impl::MaxThreads];
+ /** Probe points. */
+ typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair;
+ /** To probe when register renaming for an instruction is complete */
+ ProbePointArg<DynInstPtr> *ppRename;
+ /**
+ * To probe when an instruction is squashed and the register mapping
+ * for it needs to be undone
+ */
+ ProbePointArg<SeqNumRegPair> *ppSquashInRename;
+
public:
/** DefaultRename constructor. */
DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -129,6 +141,9 @@
/** Registers statistics. */
void regStats();
+ /** Registers probes. */
+ void regProbePoints();
+
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
diff -r 1c5102c0a7a9 -r 93d2a1526103 src/cpu/o3/rename_impl.hh
--- a/src/cpu/o3/rename_impl.hh Sat Dec 05 00:11:25 2015 +0000
+++ b/src/cpu/o3/rename_impl.hh Mon Dec 07 16:42:15 2015 -0600
@@ -186,6 +186,15 @@
template <class Impl>
void
+DefaultRename<Impl>::regProbePoints()
+{
+ ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
+ ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),
+ "SquashInRename");
+}
+
+template <class Impl>
+void
DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
timeBuffer = tb_ptr;
@@ -697,7 +706,9 @@
storesInProgress[tid]++;
}
++renamed_insts;
-
+ // Notify potential listeners that source and destination registers for
+ // this instruction have been renamed.
+ ppRename->notify(inst);
// Put instruction in rename queue.
toIEW->insts[toIEWIndex] = inst;
@@ -929,6 +940,12 @@
freeList->addReg(hb_it->newPhysReg);
}
+ // Notify potential listeners that the register mapping needs to be
+ // removed because the instruction it was mapped to got squashed. Note
+ // that this is done before hb_it is incremented.
+ ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum,
+ hb_it->newPhysReg));
+
historyBuffer[tid].erase(hb_it++);
++renameUndoneMaps;
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