changeset 9214b39401aa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9214b39401aa
description:
arm: Bootloader fix for v8 over 16 cores
Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
diffstat:
system/arm/aarch64_bootloader/boot.S | 17 +++++++++++++----
1 files changed, 13 insertions(+), 4 deletions(-)
diffs (34 lines):
diff -r 39c4dcba7131 -r 9214b39401aa system/arm/aarch64_bootloader/boot.S
--- a/system/arm/aarch64_bootloader/boot.S Fri Sep 18 16:49:28 2015 +0100
+++ b/system/arm/aarch64_bootloader/boot.S Wed Jul 15 14:43:35 2015 +0100
@@ -34,8 +34,12 @@
* registers.
*/
mrs x0, mpidr_el1
- tst x0, #15
- b.ne 1f // secondary CPU
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+ tst x0, x1 // check for cpuid==zero
+ b.ne 1f // secondary CPU
ldr x1, =GIC_DIST_BASE // GICD_CTLR
mov w0, #3 // EnableGrp0 | EnableGrp1
@@ -77,8 +81,13 @@
mov x3, xzr
mrs x4, mpidr_el1
- tst x4, #15
- b.eq 2f
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+ tst x4, x1 // check for cpuid==zero
+ mov x1, xzr // load previous 'xzr' value back to x1
+ b.eq 2f // secondary CPU
/*
* Secondary CPUs
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