changeset 4cc8b312f026 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4cc8b312f026
description:
ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically
defined
type prevents us from having types for which no machine definition may
exist.
The following changes have been made:
i. each machine definition now uses a type from the MachineType
enumeration
instead of any random identifier. This required changing the grammar
and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 2 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 2 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 2 +-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 2 +-
src/mem/protocol/MESI_Two_Level-dir.sm | 2 +-
src/mem/protocol/MESI_Two_Level-dma.sm | 2 +-
src/mem/protocol/MI_example-cache.sm | 2 +-
src/mem/protocol/MI_example-dir.sm | 2 +-
src/mem/protocol/MI_example-dma.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 2 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-dma.sm | 2 +-
src/mem/protocol/MOESI_hammer-cache.sm | 2 +-
src/mem/protocol/MOESI_hammer-dir.sm | 2 +-
src/mem/protocol/MOESI_hammer-dma.sm | 2 +-
src/mem/protocol/Network_test-cache.sm | 2 +-
src/mem/protocol/Network_test-dir.sm | 2 +-
src/mem/protocol/RubySlicc_Exports.sm | 18 ++++++++++++++++++
src/mem/slicc/ast/DeclListAST.py | 5 +----
src/mem/slicc/ast/MachineAST.py | 12 +++---------
src/mem/slicc/parser.py | 10 +++-------
src/mem/slicc/symbols/SymbolTable.py | 6 ------
src/mem/slicc/symbols/Type.py | 15 ++++++++++++---
28 files changed, 59 insertions(+), 51 deletions(-)
diffs (truncated from 440 to 300 lines):
diff -r afdcebd314be -r 4cc8b312f026
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L0Cache, "MESI Directory L0 Cache")
+machine(MachineType:L0Cache, "MESI Directory L0 Cache")
: Sequencer * sequencer;
CacheMemory * Icache;
CacheMemory * Dcache;
diff -r afdcebd314be -r 4cc8b312f026
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
: CacheMemory * cache;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "MESI Directory L2 Cache CMP")
+machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
: CacheMemory * L2cache;
Cycles l2_request_latency := 2;
Cycles l2_response_latency := 2;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm Mon Jul 20 09:15:18 2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "MESI Two Level directory protocol")
+machine(MachineType:Directory, "MESI Two Level directory protocol")
: DirectoryMemory * directory;
Cycles to_mem_ctrl_latency := 1;
Cycles directory_latency := 6;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MI Example L1 Cache")
+machine(MachineType:L1Cache, "MI Example L1 Cache")
: Sequencer * sequencer;
CacheMemory * cacheMemory;
Cycles cache_response_latency := 12;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MI_example-dir.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 12;
Cycles to_memory_controller_latency := 1;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MI_example-dma.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
diff -r afdcebd314be -r 4cc8b312f026
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "Directory protocol")
+machine(MachineType:L1Cache, "Directory protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
diff -r afdcebd314be -r 4cc8b312f026
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
: CacheMemory * L2cache;
Cycles response_latency := 2;
Cycles request_latency := 2;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 6;
Cycles to_memory_controller_latency := 1;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Mon Jul 20 09:15:18
2015 -0500
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 14;
Cycles response_latency := 14;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -31,7 +31,7 @@
*
*/
-machine(L1Cache, "Token protocol")
+machine(MachineType:L1Cache, "Token protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Mon Jul 20 09:15:18
2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
: CacheMemory * L2cache;
int N_tokens;
Cycles l2_request_latency := 5;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Mon Jul 20 09:15:18 2015 -0500
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Token protocol")
+machine(MachineType:Directory, "Token protocol")
: DirectoryMemory * directory;
int l2_select_num_bits;
Cycles directory_latency := 5;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_CMP_token-dma.sm
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Mon Jul 20 09:15:18 2015 -0500
@@ -33,7 +33,7 @@
* Brad Beckmann
*/
-machine(L1Cache, "AMD Hammer-like protocol")
+machine(MachineType:L1Cache, "AMD Hammer-like protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Mon Jul 20 09:15:18 2015 -0500
@@ -33,7 +33,7 @@
* Brad Beckmann
*/
-machine(Directory, "AMD Hammer-like protocol")
+machine(MachineType:Directory, "AMD Hammer-like protocol")
: DirectoryMemory * directory;
CacheMemory * probeFilter;
Cycles from_memory_controller_latency := 2;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/MOESI_hammer-dma.sm Mon Jul 20 09:15:18 2015 -0500
@@ -27,7 +27,7 @@
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/Network_test-cache.sm
--- a/src/mem/protocol/Network_test-cache.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/Network_test-cache.sm Mon Jul 20 09:15:18 2015 -0500
@@ -31,7 +31,7 @@
*/
-machine(L1Cache, "Network_test L1 Cache")
+machine(MachineType:L1Cache, "Network_test L1 Cache")
: Sequencer * sequencer;
Cycles issue_latency := 2;
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/Network_test-dir.sm
--- a/src/mem/protocol/Network_test-dir.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/Network_test-dir.sm Mon Jul 20 09:15:18 2015 -0500
@@ -31,7 +31,7 @@
*/
-machine(Directory, "Network_test Directory")
+machine(MachineType:Directory, "Network_test Directory")
: MessageBuffer * requestToDir, network="From", virtual_network="0",
vnet_type = "request";
MessageBuffer * forwardToDir, network="From", virtual_network="1",
diff -r afdcebd314be -r 4cc8b312f026 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/protocol/RubySlicc_Exports.sm Mon Jul 20 09:15:18 2015 -0500
@@ -173,6 +173,24 @@
Default, desc="Replace this with access_types passed to the DMA Ruby
object";
}
+
+// These are statically defined types of states machines that we can have.
+// If you want to add a new machine type, edit this enum. It is not necessary
+// for a protocol to have state machines defined for the all types here. But
+// you cannot use anything other than the ones defined here. Also, a protocol
+// can have only one state machine for a given type.
+enumeration(MachineType, desc="...", default="MachineType_NULL") {
+ L1Cache, desc="L1 Cache Mach";
+ L2Cache, desc="L2 Cache Mach";
+ L3Cache, desc="L3 Cache Mach";
+ Directory, desc="Directory Mach";
+ DMA, desc="DMA Mach";
+ Collector, desc="Collector Mach";
+ L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used
for miss latency profile)";
+ L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used
for miss latency profile)";
+ NULL, desc="null mach type";
+}
+
// MessageSizeType
enumeration(MessageSizeType, desc="...") {
Control, desc="Control Message";
diff -r afdcebd314be -r 4cc8b312f026 src/mem/slicc/ast/DeclListAST.py
--- a/src/mem/slicc/ast/DeclListAST.py Mon Jul 20 09:15:18 2015 -0500
+++ b/src/mem/slicc/ast/DeclListAST.py Mon Jul 20 09:15:18 2015 -0500
@@ -46,8 +46,5 @@
def generate(self):
for decl in self.decls:
+ decl.findMachines()
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
