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Review request for Default. Repository: gem5 Description ------- Changeset 11282:2a1dc0a50a96 --------------------------- mem: fix bug in packat access endianness changes The new Packet::setRaw() method incorrectly still contained an htog() conversion. As a result, calls to the old set() method (now defined as setRaw(htog(v))) underwent two htog conversions, which breaks things when htog() is not a no-op. Interestingly the only test that caught this was a SPARC boot test, where an IsaFake device with a non-zero return value was getting swapped twice resulting in a register getting loaded with 0x100000000000000 instead of 1. (Good reason for keeping SPARC around, perhaps?) Diffs ----- src/mem/packet_access.hh 953f7d1cc9e3 Diff: http://reviews.gem5.org/r/3264/diff/ Testing ------- Passes full regressions, makes build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test pass (with updates). Thanks, Steve Reinhardt _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
