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Review request for Default. Repository: gem5 Description ------- Changeset 11295:ffdf6dd3f3ec --------------------------- mem: Align cache behaviour in atomic when upstream is responding Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not. Diffs ----- src/mem/cache/cache.cc 57c340f947c7 Diff: http://reviews.gem5.org/r/3270/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
