changeset bce9037689b0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bce9037689b0
description:
        cpu: remove unnecessary data ptr from O3 internal read() funcs

        The read() function merely initiates a memory read operation; the
        data doesn't arrive until the access completes and a response packet
        is received from the memory system.  Thus there's no need to provide
        a data pointer; its existence is historical.

        Getting this pointer out of this internal o3 interface sets the
        stage for similar cleanup in the ExecContext interface.  Also
        found that we were pointlessly setting the contents at this pointer
        on a store forward (the useful memcpy happens just a few lines
        below the deleted one).

diffstat:

 src/cpu/base_dyn_inst.hh |   2 +-
 src/cpu/o3/cpu.hh        |   5 ++---
 src/cpu/o3/lsq.hh        |   6 +++---
 src/cpu/o3/lsq_unit.hh   |  10 ++--------
 4 files changed, 8 insertions(+), 15 deletions(-)

diffs (88 lines):

diff -r 072a171ebfb6 -r bce9037689b0 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh  Sun Jan 17 18:27:46 2016 -0800
+++ b/src/cpu/base_dyn_inst.hh  Sun Jan 17 18:27:46 2016 -0800
@@ -910,7 +910,7 @@
                 }
                 reqToVerify = new Request(*req);
             }
-            fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
+            fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
         } else {
             // Commit will have to clean up whatever happened.  Set this
             // instruction as executed.
diff -r 072a171ebfb6 -r bce9037689b0 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Sun Jan 17 18:27:46 2016 -0800
+++ b/src/cpu/o3/cpu.hh Sun Jan 17 18:27:46 2016 -0800
@@ -678,10 +678,9 @@
 
     /** CPU read function, forwards read to LSQ. */
     Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
-               uint8_t *data, int load_idx)
+               int load_idx)
     {
-        return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
-                                        data, load_idx);
+        return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
     }
 
     /** CPU write function, forwards write to LSQ. */
diff -r 072a171ebfb6 -r bce9037689b0 src/cpu/o3/lsq.hh
--- a/src/cpu/o3/lsq.hh Sun Jan 17 18:27:46 2016 -0800
+++ b/src/cpu/o3/lsq.hh Sun Jan 17 18:27:46 2016 -0800
@@ -275,7 +275,7 @@
      * index.
      */
     Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-               uint8_t *data, int load_idx);
+               int load_idx);
 
     /** Executes a store operation, using the store specified at the store
      * index.
@@ -332,11 +332,11 @@
 template <class Impl>
 Fault
 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-                uint8_t *data, int load_idx)
+                int load_idx)
 {
     ThreadID tid = req->threadId();
 
-    return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
+    return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
 }
 
 template <class Impl>
diff -r 072a171ebfb6 -r bce9037689b0 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh    Sun Jan 17 18:27:46 2016 -0800
+++ b/src/cpu/o3/lsq_unit.hh    Sun Jan 17 18:27:46 2016 -0800
@@ -511,7 +511,7 @@
   public:
     /** Executes the load at the given index. */
     Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
-               uint8_t *data, int load_idx);
+               int load_idx);
 
     /** Executes the store at the given index. */
     Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
@@ -550,7 +550,7 @@
 template <class Impl>
 Fault
 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
-                    uint8_t *data, int load_idx)
+                    int load_idx)
 {
     DynInstPtr load_inst = loadQueue[load_idx];
 
@@ -676,12 +676,6 @@
             // Get shift amount for offset into the store's data.
             int shift_amt = req->getVaddr() - 
storeQueue[store_idx].inst->effAddr;
 
-            if (storeQueue[store_idx].isAllZeros)
-                memset(data, 0, req->getSize());
-            else
-                memcpy(data, storeQueue[store_idx].data + shift_amt,
-                   req->getSize());
-
             // Allocate memory if this is the first time a load is issued.
             if (!load_inst->memData) {
                 load_inst->memData = new uint8_t[req->getSize()];
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