I also vote in favor of adding this mandate to the style guide, and enforcing it in the style checker.
-----Original Message----- From: gem5-dev [mailto:[email protected]] On Behalf Of Andreas Sandberg Sent: Friday, January 29, 2016 1:30 AM To: gem5 Developer List <[email protected]> Subject: Re: [gem5-dev] Explicit boolean comparisons (== true/== false) +1. I find explicit boolean comparisons pretty ugly myself. //Andreas On 28/01/2016, 23:19, "gem5-dev on behalf of Steve Reinhardt" <[email protected] on behalf of [email protected]> wrote: >I've noticed that some code has crept in that uses explicit boolean >comparisons in conditionals. Examples are given below. I know we've >gotten rid of these in the past (see for example >http://reviews.gem5.org/r/2281). I'd like to update the style guide to >make it clear that this is not desirable, and ideally add a check for >this to the style checker. > >Obviously some people like this style and think it improves readability. >While I personally disagree, and think that there are several reasons >why these checks aren't a good idea, I hope it's sufficient to point >out that it creates a big inconsistency when some checks are written >this way and others are not. Since we're not about to go adding these >explicit comparisons everywhere, we should consistently not use them. > >Any comments? > >Steve > > >src/cpu/base.cc: if(monitor.gotWakeup == false) { >src/cpu/base.cc.orig: if (monitor.gotWakeup == false) { >src/dev/net/dist_iface.cc: assert(recvDone->scheduled() == false); >src/dev/net/dist_iface.cc: assert(ckptRestore == false); >src/arch/x86/utility.cc: !(i > MISCREG_CR8 && i <= >MISCREG_CR15) ) == false) { >src/arch/hsail/insts/decl.hh: if (src[i].isVectorRegister() >== true) { >src/arch/hsail/insts/decl.hh: if (src0.isVectorRegister() == >true) { >src/arch/hsail/insts/decl.hh: if (src1.isVectorRegister() == >true) { >src/arch/hsail/insts/decl.hh: if (src2.isVectorRegister() == >true) { >src/arch/hsail/insts/decl.hh: if (src0.isVectorRegister() == >true) { >src/arch/hsail/insts/decl.hh: if (src1.isVectorRegister() == >true) { >src/arch/hsail/insts/mem.hh: if (src[i].isVectorRegister() >== true) { >src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc: > m_router->curCycle()) == false); >src/mem/ruby/system/GPUCoalescer.cc: if (deadlockCheckEvent.scheduled() >== false) { >src/mem/ruby/common/WriteMask.hh: return mMask[offset] == true; >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
