changeset 42ecb523c64a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=42ecb523c64a
description:
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
diffstat:
configs/common/CacheConfig.py | 4 +-
configs/common/Simulation.py | 2 +-
configs/example/ruby_mem_test.py | 2 +-
src/arch/alpha/isa/decoder.isa | 24 +-
src/arch/alpha/linux/linux.hh | 2 +-
src/arch/alpha/process.cc | 8 +-
src/arch/alpha/tlb.cc | 6 +-
src/arch/arm/SConscript | 2 +-
src/arch/arm/interrupts.cc | 2 +-
src/arch/arm/isa/bitfields.isa | 2 +-
src/arch/arm/isa/formats/pred.isa | 16 +-
src/arch/arm/linux/linux.hh | 2 +-
src/arch/arm/stacktrace.cc | 2 +-
src/arch/mips/isa/decoder.isa | 6 +-
src/arch/mips/linux/linux.hh | 4 +-
src/arch/mips/linux/process.cc | 2 +-
src/arch/mips/pagetable.hh | 2 +-
src/arch/power/SConscript | 2 +-
src/arch/sparc/interrupts.cc | 2 +-
src/arch/sparc/linux/linux.hh | 8 +-
src/arch/sparc/pagetable.hh | 2 +-
src/arch/x86/cpuid.cc | 2 +-
src/arch/x86/faults.cc | 2 +-
src/arch/x86/insts/micromediaop.hh | 2 +-
src/arch/x86/isa/insts/general_purpose/system_calls.py | 4 +-
src/arch/x86/isa/insts/romutil.py | 8 +-
src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py | 2 +-
src/arch/x86/isa/microops/base.isa | 2 +-
src/arch/x86/isa/microops/mediaop.isa | 10 +-
src/arch/x86/isa/microops/regop.isa | 6 +-
src/arch/x86/process.cc | 2 +-
src/arch/x86/process.hh | 2 +-
src/base/cp_annotate.cc | 26 +-
src/base/cp_annotate.hh | 84 +++++-----
src/base/cprintf.hh | 4 +-
src/base/flags.hh | 4 +-
src/base/inet.cc | 2 +-
src/base/inet.hh | 2 +-
src/base/loader/ecoff_object.cc | 2 +-
src/base/loader/elf_object.cc | 2 +-
src/base/statistics.cc | 2 +-
src/cpu/o3/decode_impl.hh | 2 +-
src/cpu/simple/timing.cc | 4 +-
src/cpu/testers/directedtest/DirectedGenerator.cc | 2 +-
src/cpu/testers/directedtest/DirectedGenerator.hh | 10 +-
src/cpu/testers/directedtest/InvalidateGenerator.cc | 8 +-
src/cpu/testers/directedtest/InvalidateGenerator.hh | 10 +-
src/cpu/testers/directedtest/RubyDirectedTester.cc | 4 +-
src/cpu/testers/directedtest/SeriesRequestGenerator.cc | 4 +-
src/cpu/testers/directedtest/SeriesRequestGenerator.hh | 10 +-
src/cpu/testers/networktest/networktest.cc | 8 +-
src/cpu/timebuf.hh | 2 +-
src/dev/mc146818.cc | 2 +-
src/dev/net/i8254xGBe.cc | 70 ++++----
src/dev/net/i8254xGBe.hh | 6 +-
src/dev/net/i8254xGBe_defs.hh | 14 +-
src/dev/x86/i8042.cc | 2 +-
src/dev/x86/i8254.hh | 4 +-
src/dev/x86/intdev.hh | 2 +-
src/mem/mport.hh | 2 +-
src/mem/ruby/network/Topology.cc | 12 +-
src/mem/ruby/network/Topology.hh | 2 +-
src/mem/ruby/network/fault_model/FaultModel.cc | 62 +++---
src/mem/ruby/network/fault_model/FaultModel.hh | 26 +-
src/mem/ruby/network/fault_model/FaultModel.py | 6 +-
src/mem/ruby/network/fault_model/SConscript | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh | 16 +-
src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py | 2 +-
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh | 10 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.hh | 6 +-
src/mem/ruby/network/simple/SimpleLink.cc | 12 +-
src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 +-
src/mem/slicc/ast/TypeFieldEnumAST.py | 2 +-
src/mem/slicc/ast/TypeFieldStateAST.py | 2 +-
src/python/m5/util/__init__.py | 2 +-
src/python/swig/event.i | 4 +-
src/sim/Root.py | 2 +-
src/sim/eventq.cc | 6 +-
src/sim/eventq.hh | 2 +-
src/sim/insttracer.hh | 2 +-
src/sim/pseudo_inst.cc | 4 +-
src/unittest/cprintftest.cc | 2 +-
system/alpha/console/console.c | 2 +-
tests/configs/memtest-ruby.py | 2 +-
util/checkpoint-tester.py | 4 +-
util/compile | 2 +-
util/m5/m5.c | 4 +-
util/qdo | 18 +-
util/statetrace/SConstruct | 2 +-
90 files changed, 330 insertions(+), 330 deletions(-)
diffs (truncated from 2562 to 300 lines):
diff -r 7ca84595249c -r 42ecb523c64a configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Sat Feb 06 17:21:18 2016 -0800
+++ b/configs/common/CacheConfig.py Sat Feb 06 17:21:18 2016 -0800
@@ -1,6 +1,6 @@
# Copyright (c) 2012-2013, 2015 ARM Limited
# All rights reserved
-#
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
@@ -9,7 +9,7 @@
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
-#
+#
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
diff -r 7ca84595249c -r 42ecb523c64a configs/common/Simulation.py
--- a/configs/common/Simulation.py Sat Feb 06 17:21:18 2016 -0800
+++ b/configs/common/Simulation.py Sat Feb 06 17:21:18 2016 -0800
@@ -1,6 +1,6 @@
# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
-#
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
diff -r 7ca84595249c -r 42ecb523c64a configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Sat Feb 06 17:21:18 2016 -0800
+++ b/configs/example/ruby_mem_test.py Sat Feb 06 17:21:18 2016 -0800
@@ -142,7 +142,7 @@
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
-
+
assert(len(cpus) == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(cpus):
diff -r 7ca84595249c -r 42ecb523c64a src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/alpha/isa/decoder.isa Sat Feb 06 17:21:18 2016 -0800
@@ -349,7 +349,7 @@
for (int i = 0; i < 8; ++i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
- temp += (ra_ub >= rb_ub) ?
+ temp += (ra_ub >= rb_ub) ?
(ra_ub - rb_ub) : (rb_ub - ra_ub);
hi += 8;
lo += 8;
@@ -378,15 +378,15 @@
if (!(temp<7:0>)) { temp >>= 8; count += 8; }
if (!(temp<3:0>)) { temp >>= 4; count += 4; }
if (!(temp<1:0>)) { temp >>= 2; count += 2; }
- if (!(temp<0:0> & ULL(0x1))) {
- temp >>= 1; count += 1;
+ if (!(temp<0:0> & ULL(0x1))) {
+ temp >>= 1; count += 1;
}
if (!(temp<0:0> & ULL(0x1))) count += 1;
Rc = count;
}}, IntAluOp);
- 0x34: unpkbw({{
+ 0x34: unpkbw({{
Rc = (Rb_uq<7:0>
| (Rb_uq<15:8> << 16)
| (Rb_uq<23:16> << 32)
@@ -415,7 +415,7 @@
for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb_uq<hi:lo>;
- temp = ((temp << 8)
+ temp = ((temp << 8)
| ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -431,7 +431,7 @@
for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
+ temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -447,7 +447,7 @@
for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
- temp = ((temp << 8)
+ temp = ((temp << 8)
| ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -463,7 +463,7 @@
for (int i = 3; i >= 0; --i) {
uint16_t ra_sw = Ra_uq<hi:lo>;
uint16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
+ temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -479,7 +479,7 @@
for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
- temp = ((temp << 8)
+ temp = ((temp << 8)
| ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -495,7 +495,7 @@
for (int i = 3; i >= 0; --i) {
uint16_t ra_uw = Ra_uq<hi:lo>;
uint16_t rb_uw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
+ temp = ((temp << 16)
| ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -511,7 +511,7 @@
for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb_uq<hi:lo>;
- temp = ((temp << 8)
+ temp = ((temp << 8)
| ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -527,7 +527,7 @@
for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
+ temp = ((temp << 16)
| ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
diff -r 7ca84595249c -r 42ecb523c64a src/arch/alpha/linux/linux.hh
--- a/src/arch/alpha/linux/linux.hh Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/alpha/linux/linux.hh Sat Feb 06 17:21:18 2016 -0800
@@ -127,7 +127,7 @@
static const unsigned TGT_RLIMIT_AS = 7;
static const unsigned TGT_RLIMIT_NOFILE = 6;
static const unsigned TGT_RLIMIT_MEMLOCK = 9;
-
+
typedef struct {
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
diff -r 7ca84595249c -r 42ecb523c64a src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/alpha/process.cc Sat Feb 06 17:21:18 2016 -0800
@@ -75,7 +75,7 @@
ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
if(elfObject)
{
- // modern glibc uses a bunch of auxiliary vectors to set up
+ // modern glibc uses a bunch of auxiliary vectors to set up
// TLS as well as do a bunch of other stuff
// these vectors go on the bottom of the stack, below argc/argv/envp
// pointers but above actual arg strings
@@ -111,10 +111,10 @@
}
int space_needed =
- argv_array_size +
- envp_array_size +
+ argv_array_size +
+ envp_array_size +
auxv_array_size +
- arg_data_size +
+ arg_data_size +
env_data_size;
if (space_needed < 32*1024)
diff -r 7ca84595249c -r 42ecb523c64a src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/alpha/tlb.cc Sat Feb 06 17:21:18 2016 -0800
@@ -230,9 +230,9 @@
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
}
// We shouldn't be able to read from an uncachable address in Alpha as
- // we don't have a ROM and we don't want to try to fetch from a device
- // register as we destroy any data that is clear-on-read.
- if (req->isUncacheable() && itb)
+ // we don't have a ROM and we don't want to try to fetch from a device
+ // register as we destroy any data that is clear-on-read.
+ if (req->isUncacheable() && itb)
return std::make_shared<UnimpFault>(
"CPU trying to fetch from uncached I/O");
diff -r 7ca84595249c -r 42ecb523c64a src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/SConscript Sat Feb 06 17:21:18 2016 -0800
@@ -45,7 +45,7 @@
if env['TARGET_ISA'] == 'arm':
# Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308
+# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
Source('faults.cc')
diff -r 7ca84595249c -r 42ecb523c64a src/arch/arm/interrupts.cc
--- a/src/arch/arm/interrupts.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/interrupts.cc Sat Feb 06 17:21:18 2016 -0800
@@ -39,7 +39,7 @@
#include "arch/arm/interrupts.hh"
#include "arch/arm/system.hh"
-
+
ArmISA::Interrupts *
ArmInterruptsParams::create()
{
diff -r 7ca84595249c -r 42ecb523c64a src/arch/arm/isa/bitfields.isa
--- a/src/arch/arm/isa/bitfields.isa Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/isa/bitfields.isa Sat Feb 06 17:21:18 2016 -0800
@@ -65,7 +65,7 @@
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
-def bitfield OPC2 opc2;
+def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_6 opcode6;
def bitfield OPCODE_4 opcode4;
diff -r 7ca84595249c -r 42ecb523c64a src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/isa/formats/pred.isa Sat Feb 06 17:21:18 2016 -0800
@@ -41,7 +41,7 @@
// Authors: Stephen Hines
let {{
-
+
calcCcCode = '''
if (%(canOverflow)s){
cprintf("canOverflow: %%d\\n", Rd < resTemp);
@@ -52,7 +52,7 @@
_iz = (resTemp == 0);
_iv = %(ivValue)s;
_ic = %(icValue)s;
-
+
CondCodesNZ = (_in << 1) | (_iz);
CondCodesC = _ic;
CondCodesV = _iv;
@@ -79,7 +79,7 @@
iv = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
- canOverflow = "true"
+ canOverflow = "true"
icReg = icImm = iv = '0'
elif flagtype == "add":
icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
@@ -94,12 +94,12 @@
icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
iv = 'CondCodesV'
- return (calcCcCode % {"icValue" : icReg,
- "ivValue" : iv,
+ return (calcCcCode % {"icValue" : icReg,
+ "ivValue" : iv,
"negBit" : negBit,
"canOverflow" : canOverflow },
- calcCcCode % {"icValue" : icImm,
- "ivValue" : iv,
+ calcCcCode % {"icValue" : icImm,
+ "ivValue" : iv,
"negBit" : negBit,
"canOverflow" : canOverflow })
@@ -116,7 +116,7 @@
negBit = 63
elif flagtype == "overflow":
icVaule = ivValue = '0'
- canOverflow = "true"
+ canOverflow = "true"
elif flagtype == "add":
icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
diff -r 7ca84595249c -r 42ecb523c64a src/arch/arm/linux/linux.hh
--- a/src/arch/arm/linux/linux.hh Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/linux/linux.hh Sat Feb 06 17:21:18 2016 -0800
@@ -177,7 +177,7 @@
uint32_t freehigh; /* Available high memory size */
uint32_t mem_unit; /* Memory unit size in bytes */
} tgt_sysinfo;
-
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