changeset 02e930db812d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=02e930db812d
description:
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
diffstat:
src/arch/alpha/process.cc | 2 +-
src/arch/arm/insts/macromem.cc | 14 ++--
src/arch/arm/insts/vfp.hh | 10 +-
src/arch/arm/kvm/arm_cpu.cc | 2 +-
src/arch/arm/linux/system.cc | 4 +-
src/arch/arm/tlb.cc | 6 +-
src/arch/generic/tlb.cc | 2 +-
src/arch/mips/isa.cc | 2 +-
src/arch/x86/bios/intelmp.cc | 2 +-
src/arch/x86/cpuid.cc | 2 +-
src/arch/x86/decoder.cc | 18 +++---
src/arch/x86/insts/microldstop.cc | 2 +-
src/arch/x86/insts/microregop.cc | 20 +++---
src/arch/x86/insts/static_inst.cc | 14 ++--
src/arch/x86/insts/static_inst.hh | 6 +-
src/arch/x86/nativetrace.cc | 10 +-
src/arch/x86/pagetable_walker.cc | 4 +-
src/arch/x86/process.cc | 6 +-
src/arch/x86/types.hh | 26
+++++-----
src/base/atomicio.hh | 2 +-
src/base/cp_annotate.cc | 2 +-
src/base/fenv.c | 2 +-
src/base/loader/elf_object.cc | 8 +-
src/base/statistics.cc | 4 +-
src/cpu/base.cc | 8 +-
src/cpu/kvm/perfevent.cc | 2 +-
src/cpu/kvm/x86_cpu.cc | 10 +-
src/cpu/minor/decode.cc | 2 +-
src/cpu/nativetrace.cc | 2 +-
src/cpu/nativetrace.hh | 2 +-
src/cpu/o3/inst_queue_impl.hh | 2 +-
src/cpu/o3/rename_impl.hh | 2 +-
src/cpu/pred/bpred_unit.cc | 2 +-
src/cpu/simple/atomic.cc | 12 ++--
src/cpu/simple/base.cc | 2 +-
src/cpu/simple/timing.cc | 4 +-
src/dev/alpha/tsunami_cchip.cc | 20 +++---
src/dev/arm/flash_device.cc | 4 +-
src/dev/arm/ufs_device.cc | 16 +++---
src/dev/intel_8254_timer.cc | 4 +-
src/dev/mips/malta_cchip.cc | 20 +++---
src/dev/virtio/base.cc | 12 ++--
src/mem/bridge.cc | 2 +-
src/mem/cache/prefetch/stride.cc | 2 +-
src/mem/dram_ctrl.cc | 12 ++--
src/mem/physical.cc | 2 +-
src/mem/port.cc | 4 +-
src/mem/ruby/filters/BulkBloomFilter.cc | 2 +-
src/mem/ruby/filters/H3BloomFilter.cc | 4 +-
src/mem/ruby/filters/MultiBitSelBloomFilter.cc | 2 +-
src/mem/ruby/filters/MultiGrainBloomFilter.cc | 4 +-
src/mem/ruby/filters/NonCountingBloomFilter.cc | 2 +-
src/mem/ruby/network/MessageBuffer.cc | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc | 4 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 2 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 4 +-
src/mem/ruby/profiler/AccessTraceForAddress.cc | 4 +-
src/mem/ruby/slicc_interface/AbstractController.cc | 2 +-
src/mem/ruby/structures/AbstractReplacementPolicy.cc | 4 +-
src/mem/ruby/structures/BankedArray.cc | 2 +-
src/mem/ruby/structures/CacheMemory.cc | 10 +-
src/mem/ruby/structures/PseudoLRUPolicy.cc | 2 +-
src/mem/ruby/structures/RubyMemoryControl.cc | 2 +-
src/mem/ruby/structures/TBETable.hh | 2 +-
src/mem/ruby/system/GPUCoalescer.cc | 20 +++---
src/mem/ruby/system/Sequencer.cc | 2 +-
src/mem/ruby/system/VIPERCoalescer.cc | 6 +-
src/mem/ruby/system/WeightedLRUPolicy.cc | 4 +-
src/mem/serial_link.cc | 2 +-
src/mem/stack_dist_calc.cc | 4 +-
src/python/swig/pyobject.cc | 2 +-
src/sim/backtrace_glibc.cc | 2 +-
src/sim/dvfs_handler.cc | 4 +-
src/sim/serialize.hh | 2 +-
src/sim/syscall_emul.hh | 6 +-
tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl | 2 +-
tests/test-progs/gpu-hello/src/gpu-hello.cpp | 4 +-
tests/test-progs/mwait/mwait.c | 8 +-
util/statetrace/arch/amd64/tracechild.cc | 10 +-
util/statetrace/arch/arm/tracechild.cc | 12 ++--
util/statetrace/arch/sparc/tracechild.cc | 6 +-
util/tlm/main.cc | 2 +-
util/tlm/sc_mm.cc | 4 +-
util/tlm/sc_port.cc | 12 ++--
util/tlm/sc_target.cc | 12 ++--
85 files changed, 249 insertions(+), 249 deletions(-)
diffs (truncated from 2208 to 300 lines):
diff -r 42ecb523c64a -r 02e930db812d src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/alpha/process.cc Sat Feb 06 17:21:19 2016 -0800
@@ -73,7 +73,7 @@
std::vector<auxv_t> auxv;
ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
- if(elfObject)
+ if (elfObject)
{
// modern glibc uses a bunch of auxiliary vectors to set up
// TLS as well as do a bunch of other stuff
diff -r 42ecb523c64a -r 02e930db812d src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/insts/macromem.cc Sat Feb 06 17:21:19 2016 -0800
@@ -145,7 +145,7 @@
// 32-bit memory operation
// Find register for operation
unsigned reg_idx;
- while(!bits(regs, reg)) reg++;
+ while (!bits(regs, reg)) reg++;
replaceBits(regs, reg, 0);
reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg;
@@ -1149,7 +1149,7 @@
TLB::AllowUnaligned;
int i = 0;
- for(; i < numMemMicroops - 1; ++i) {
+ for (; i < numMemMicroops - 1; ++i) {
microOps[uopIdx++] = new MicroNeonLoad64(
machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
baseIsSP, 16 /* accSize */, eSize);
@@ -1231,7 +1231,7 @@
microOps = new StaticInstPtr[numMicroops];
unsigned uopIdx = 0;
- for(int i = 0; i < numMarshalMicroops; ++i) {
+ for (int i = 0; i < numMarshalMicroops; ++i) {
switch (numRegs) {
case 1: microOps[uopIdx++] = new MicroIntNeon64_1Reg(
machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
@@ -1257,7 +1257,7 @@
TLB::AllowUnaligned;
int i = 0;
- for(; i < numMemMicroops - 1; ++i) {
+ for (; i < numMemMicroops - 1; ++i) {
microOps[uopIdx++] = new MicroNeonStore64(
machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
baseIsSP, 16 /* accSize */, eSize);
@@ -1347,7 +1347,7 @@
}
}
- for(int i = 0; i < numMarshalMicroops; ++i) {
+ for (int i = 0; i < numMarshalMicroops; ++i) {
microOps[uopIdx++] = new MicroUnpackNeon64(
machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
numStructElems, index, i /* step */, replicate);
@@ -1394,7 +1394,7 @@
microOps = new StaticInstPtr[numMicroops];
unsigned uopIdx = 0;
- for(int i = 0; i < numMarshalMicroops; ++i) {
+ for (int i = 0; i < numMarshalMicroops; ++i) {
microOps[uopIdx++] = new MicroPackNeon64(
machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
numStructElems, index, i /* step */, replicate);
@@ -1404,7 +1404,7 @@
TLB::AllowUnaligned;
int i = 0;
- for(; i < numMemMicroops - 1; ++i) {
+ for (; i < numMemMicroops - 1; ++i) {
microOps[uopIdx++] = new MicroNeonStore64(
machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
baseIsSP, 16 /* accsize */, eSize);
diff -r 42ecb523c64a -r 02e930db812d src/arch/arm/insts/vfp.hh
--- a/src/arch/arm/insts/vfp.hh Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/insts/vfp.hh Sat Feb 06 17:21:19 2016 -0800
@@ -551,7 +551,7 @@
bool zero1 = (std::fpclassify(a) == FP_ZERO);
bool zero2 = (std::fpclassify(b) == FP_ZERO);
if ((inf1 && zero2) || (zero1 && inf2)) {
- if(sign1 ^ sign2)
+ if (sign1 ^ sign2)
return (T)(-2.0);
else
return (T)(2.0);
@@ -685,7 +685,7 @@
}
aXb = a*b;
fpClassAxB = std::fpclassify(aXb);
- if(fpClassAxB == FP_SUBNORMAL) {
+ if (fpClassAxB == FP_SUBNORMAL) {
feraiseexcept(FeUnderflow);
return 1.5;
}
@@ -707,7 +707,7 @@
}
aXb = a*b;
fpClassAxB = std::fpclassify(aXb);
- if(fpClassAxB == FP_SUBNORMAL) {
+ if (fpClassAxB == FP_SUBNORMAL) {
feraiseexcept(FeUnderflow);
return 2.0;
}
@@ -729,7 +729,7 @@
}
aXb = a*b;
fpClassAxB = std::fpclassify(aXb);
- if(fpClassAxB == FP_SUBNORMAL) {
+ if (fpClassAxB == FP_SUBNORMAL) {
feraiseexcept(FeUnderflow);
return 1.5;
}
@@ -750,7 +750,7 @@
}
aXb = a*b;
fpClassAxB = std::fpclassify(aXb);
- if(fpClassAxB == FP_SUBNORMAL) {
+ if (fpClassAxB == FP_SUBNORMAL) {
feraiseexcept(FeUnderflow);
return 2.0;
}
diff -r 42ecb523c64a -r 02e930db812d src/arch/arm/kvm/arm_cpu.cc
--- a/src/arch/arm/kvm/arm_cpu.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/kvm/arm_cpu.cc Sat Feb 06 17:21:19 2016 -0800
@@ -399,7 +399,7 @@
default:
return NUM_MISCREGS;
}
- } else if(is_reg64) {
+ } else if (is_reg64) {
return NUM_MISCREGS;
} else {
warn("Unhandled register length, register (0x%x) ignored.\n");
diff -r 42ecb523c64a -r 02e930db812d src/arch/arm/linux/system.cc
--- a/src/arch/arm/linux/system.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/linux/system.cc Sat Feb 06 17:21:19 2016 -0800
@@ -83,7 +83,7 @@
// newer kernels use __loop_udelay and __loop_const_udelay symbols
uDelaySkipEvent = addKernelFuncEvent<UDelayEvent>(
"__loop_udelay", "__udelay", 1000, 0);
- if(!uDelaySkipEvent)
+ if (!uDelaySkipEvent)
uDelaySkipEvent = addKernelFuncEventOrPanic<UDelayEvent>(
"__udelay", "__udelay", 1000, 0);
@@ -91,7 +91,7 @@
// time. Constant comes from code.
constUDelaySkipEvent = addKernelFuncEvent<UDelayEvent>(
"__loop_const_udelay", "__const_udelay", 1000, 107374);
- if(!constUDelaySkipEvent)
+ if (!constUDelaySkipEvent)
constUDelaySkipEvent = addKernelFuncEventOrPanic<UDelayEvent>(
"__const_udelay", "__const_udelay", 1000, 107374);
diff -r 42ecb523c64a -r 02e930db812d src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/arm/tlb.cc Sat Feb 06 17:21:19 2016 -0800
@@ -148,7 +148,7 @@
// than rangeMRU
if (x > rangeMRU && !functional) {
TlbEntry tmp_entry = table[x];
- for(int i = x; i > 0; i--)
+ for (int i = x; i > 0; i--)
table[i] = table[i - 1];
table[0] = tmp_entry;
retval = &table[0];
@@ -394,7 +394,7 @@
int num_entries = size;
SERIALIZE_SCALAR(num_entries);
- for(int i = 0; i < size; i++)
+ for (int i = 0; i < size; i++)
table[i].serializeSection(cp, csprintf("TlbEntry%d", i));
}
@@ -410,7 +410,7 @@
int num_entries;
UNSERIALIZE_SCALAR(num_entries);
- for(int i = 0; i < min(size, num_entries); i++)
+ for (int i = 0; i < min(size, num_entries); i++)
table[i].unserializeSection(cp, csprintf("TlbEntry%d", i));
}
diff -r 42ecb523c64a -r 02e930db812d src/arch/generic/tlb.cc
--- a/src/arch/generic/tlb.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/generic/tlb.cc Sat Feb 06 17:21:19 2016 -0800
@@ -45,7 +45,7 @@
Process * p = tc->getProcessPtr();
Fault fault = p->pTable->translate(req);
- if(fault != NoFault)
+ if (fault != NoFault)
return fault;
return NoFault;
diff -r 42ecb523c64a -r 02e930db812d src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/mips/isa.cc Sat Feb 06 17:21:19 2016 -0800
@@ -150,7 +150,7 @@
void
ISA::clear()
{
- for(int i = 0; i < NumMiscRegs; i++) {
+ for (int i = 0; i < NumMiscRegs; i++) {
for (int j = 0; j < miscRegFile[i].size(); j++)
miscRegFile[i][j] = 0;
diff -r 42ecb523c64a -r 02e930db812d src/arch/x86/bios/intelmp.cc
--- a/src/arch/x86/bios/intelmp.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/x86/bios/intelmp.cc Sat Feb 06 17:21:19 2016 -0800
@@ -76,7 +76,7 @@
proxy.writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
uint8_t checkSum = 0;
- while(guestVal) {
+ while (guestVal) {
checkSum += guestVal;
guestVal >>= 8;
}
diff -r 42ecb523c64a -r 02e930db812d src/arch/x86/cpuid.cc
--- a/src/arch/x86/cpuid.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/x86/cpuid.cc Sat Feb 06 17:21:19 2016 -0800
@@ -142,7 +142,7 @@
funcNum);
return false;
}
- } else if(family == 0x0000) {
+ } else if (family == 0x0000) {
// The standard functions
switch (funcNum) {
case VendorAndLargestStdFunc:
diff -r 42ecb523c64a -r 02e930db812d src/arch/x86/decoder.cc
--- a/src/arch/x86/decoder.cc Sat Feb 06 17:21:18 2016 -0800
+++ b/src/arch/x86/decoder.cc Sat Feb 06 17:21:19 2016 -0800
@@ -386,7 +386,7 @@
//Figure out the effective address size. This can be overriden to
//a fixed value at the decoder level.
int logAddrSize;
- if(emi.legacy.addr)
+ if (emi.legacy.addr)
logAddrSize = altAddr;
else
logAddrSize = defAddr;
@@ -410,7 +410,7 @@
if (modrmTable[opcode]) {
nextState = ModRMState;
} else {
- if(immediateSize) {
+ if (immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
@@ -439,7 +439,7 @@
//Figure out the effective address size. This can be overriden to
//a fixed value at the decoder level.
int logAddrSize;
- if(emi.legacy.addr)
+ if (emi.legacy.addr)
logAddrSize = altAddr;
else
logAddrSize = defAddr;
@@ -509,9 +509,9 @@
if (modRM.rm == 4 && modRM.mod != 3) {
// && in 32/64 bit mode)
nextState = SIBState;
- } else if(displacementSize) {
+ } else if (displacementSize) {
nextState = DisplacementState;
- } else if(immediateSize) {
+ } else if (immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
@@ -537,7 +537,7 @@
displacementSize = 4;
if (displacementSize) {
nextState = DisplacementState;
- } else if(immediateSize) {
+ } else if (immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
@@ -560,7 +560,7 @@
DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
displacementSize, immediateCollected);
- if(displacementSize == immediateCollected) {
+ if (displacementSize == immediateCollected) {
//Reset this for other immediates.
immediateCollected = 0;
//Sign extend the displacement
@@ -580,7 +580,7 @@
}
DPRINTF(Decoder, "Collected displacement %#x.\n",
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