changeset 67cc559d513a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67cc559d513a
description:
style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.
Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) ==
true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
diffstat:
src/arch/hsail/gen.py | 2 +-
src/arch/hsail/insts/decl.hh | 12 ++++++------
src/arch/hsail/insts/mem.hh | 2 +-
src/cpu/base.cc | 2 +-
src/dev/net/dist_iface.cc | 4 ++--
src/mem/ruby/common/WriteMask.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc | 4 ++--
src/mem/ruby/system/GPUCoalescer.cc | 2 +-
src/mem/slicc/symbols/Transition.py | 2 +-
9 files changed, 16 insertions(+), 16 deletions(-)
diffs (142 lines):
diff -r 31ca646c7685 -r 67cc559d513a src/arch/hsail/gen.py
--- a/src/arch/hsail/gen.py Sat Feb 06 17:21:20 2016 -0800
+++ b/src/arch/hsail/gen.py Sat Feb 06 17:21:20 2016 -0800
@@ -584,7 +584,7 @@
else:
decoder_code(decode_case_prolog)
if not type2_info:
- if is_store == False:
+ if not is_store:
# single list of types, to basic one-level decode
for type_name in types:
full_class_name = '%s<%s>' % (class_name,
type_name.upper())
diff -r 31ca646c7685 -r 67cc559d513a src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh Sat Feb 06 17:21:20 2016 -0800
+++ b/src/arch/hsail/insts/decl.hh Sat Feb 06 17:21:20 2016 -0800
@@ -189,7 +189,7 @@
int numSrcRegOperands() {
int operands = 0;
for (int i = 0; i < NumSrcOperands; i++) {
- if (src[i].isVectorRegister() == true) {
+ if (src[i].isVectorRegister()) {
operands++;
}
}
@@ -325,13 +325,13 @@
int numSrcRegOperands() {
int operands = 0;
- if (src0.isVectorRegister() == true) {
+ if (src0.isVectorRegister()) {
operands++;
}
- if (src1.isVectorRegister() == true) {
+ if (src1.isVectorRegister()) {
operands++;
}
- if (src2.isVectorRegister() == true) {
+ if (src2.isVectorRegister()) {
operands++;
}
return operands;
@@ -485,10 +485,10 @@
int numSrcRegOperands() {
int operands = 0;
- if (src0.isVectorRegister() == true) {
+ if (src0.isVectorRegister()) {
operands++;
}
- if (src1.isVectorRegister() == true) {
+ if (src1.isVectorRegister()) {
operands++;
}
return operands;
diff -r 31ca646c7685 -r 67cc559d513a src/arch/hsail/insts/mem.hh
--- a/src/arch/hsail/insts/mem.hh Sat Feb 06 17:21:20 2016 -0800
+++ b/src/arch/hsail/insts/mem.hh Sat Feb 06 17:21:20 2016 -0800
@@ -1239,7 +1239,7 @@
{
int operands = 0;
for (int i = 0; i < NumSrcOperands; i++) {
- if (src[i].isVectorRegister() == true) {
+ if (src[i].isVectorRegister()) {
operands++;
}
}
diff -r 31ca646c7685 -r 67cc559d513a src/cpu/base.cc
--- a/src/cpu/base.cc Sat Feb 06 17:21:20 2016 -0800
+++ b/src/cpu/base.cc Sat Feb 06 17:21:20 2016 -0800
@@ -288,7 +288,7 @@
assert(tid < numThreads);
AddressMonitor &monitor = addressMonitor[tid];
- if (monitor.gotWakeup == false) {
+ if (!monitor.gotWakeup) {
int block_size = cacheLineSize();
uint64_t mask = ~((uint64_t)(block_size - 1));
diff -r 31ca646c7685 -r 67cc559d513a src/dev/net/dist_iface.cc
--- a/src/dev/net/dist_iface.cc Sat Feb 06 17:21:20 2016 -0800
+++ b/src/dev/net/dist_iface.cc Sat Feb 06 17:21:20 2016 -0800
@@ -517,8 +517,8 @@
DistIface::RecvScheduler::unserialize(CheckpointIn &cp)
{
assert(descQueue.size() == 0);
- assert(recvDone->scheduled() == false);
- assert(ckptRestore == false);
+ assert(!recvDone->scheduled());
+ assert(!ckptRestore);
UNSERIALIZE_SCALAR(prevRecvTick);
// unserialize the receive desc queue
diff -r 31ca646c7685 -r 67cc559d513a src/mem/ruby/common/WriteMask.hh
--- a/src/mem/ruby/common/WriteMask.hh Sat Feb 06 17:21:20 2016 -0800
+++ b/src/mem/ruby/common/WriteMask.hh Sat Feb 06 17:21:20 2016 -0800
@@ -71,7 +71,7 @@
test(int offset)
{
assert(offset < mSize);
- return mMask[offset] == true;
+ return mMask[offset];
}
void
diff -r 31ca646c7685 -r 67cc559d513a
src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc Sat Feb
06 17:21:20 2016 -0800
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc Sat Feb
06 17:21:20 2016 -0800
@@ -188,8 +188,8 @@
m_router->curCycle());
// This Input VC should now be empty
- assert(m_input_unit[inport]->isReady(invc,
- m_router->curCycle()) == false);
+ assert(!m_input_unit[inport]->
+ isReady(invc, m_router->curCycle()));
m_input_unit[inport]->set_vc_state(IDLE_, invc,
m_router->curCycle());
diff -r 31ca646c7685 -r 67cc559d513a src/mem/ruby/system/GPUCoalescer.cc
--- a/src/mem/ruby/system/GPUCoalescer.cc Sat Feb 06 17:21:20 2016 -0800
+++ b/src/mem/ruby/system/GPUCoalescer.cc Sat Feb 06 17:21:20 2016 -0800
@@ -320,7 +320,7 @@
assert(m_outstanding_count == total_outstanding);
// See if we should schedule a deadlock check
- if (deadlockCheckEvent.scheduled() == false) {
+ if (!deadlockCheckEvent.scheduled()) {
schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
}
diff -r 31ca646c7685 -r 67cc559d513a src/mem/slicc/symbols/Transition.py
--- a/src/mem/slicc/symbols/Transition.py Sat Feb 06 17:21:20 2016 -0800
+++ b/src/mem/slicc/symbols/Transition.py Sat Feb 06 17:21:20 2016 -0800
@@ -43,7 +43,7 @@
if func.c_ident == 'getNextState_Addr':
found = True
break
- if found == False:
+ if not found:
fatal("Machine uses a wildcard transition without getNextState
defined")
self.nextState = WildcardState(machine.symtab,
'*', location)
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
