changeset 1e7b883dffc6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1e7b883dffc6 description: arch: get rid of dummy var init
MemOperand variables were being initialized to 0 "to avoid 'uninitialized variable' errors" but these no longer seem to be a problem (with the exception of one use case in POWER that is arguably broken and easily fixed here). Getting rid of the initialization is necessary to set up a subsequent patch which extends memory operands to possibly not be scalars, making the '= 0' initialization no longer feasible. diffstat: src/arch/isa_parser.py | 4 +--- src/arch/power/isa/decoder.isa | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diffs (30 lines): diff -r cc2f9e13694d -r 1e7b883dffc6 src/arch/isa_parser.py --- a/src/arch/isa_parser.py Sat Feb 06 17:21:20 2016 -0800 +++ b/src/arch/isa_parser.py Sat Feb 06 17:21:20 2016 -0800 @@ -790,10 +790,8 @@ return '' def makeDecl(self): - # Note that initializations in the declarations are solely - # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - return '%s %s = 0;\n' % (self.ctype, self.base_name) + return '%s %s;\n' % (self.ctype, self.base_name) def makeRead(self, predRead): if self.read_code != None: diff -r cc2f9e13694d -r 1e7b883dffc6 src/arch/power/isa/decoder.isa --- a/src/arch/power/isa/decoder.isa Sat Feb 06 17:21:20 2016 -0800 +++ b/src/arch/power/isa/decoder.isa Sat Feb 06 17:21:20 2016 -0800 @@ -309,10 +309,10 @@ 151: stwx({{ Mem = Rs; }}); 150: stwcx({{ bool store_performed = false; + Mem = Rs; if (Rsv) { if (RsvLen == 4) { if (RsvAddr == EA) { - Mem = Rs; store_performed = true; } } _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev