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Review request for Default. Repository: gem5 Description ------- arm: Squash after returning from exceptions in v7 Properly done for the ERET instruction in v8, but not for v7. Many control register changes are only visible after explicit instruction synchronization barriers or exception entry/exit. This means mode changing instructions should squash any younger in-flight speculative instructions. Diffs ----- src/arch/arm/isa/insts/data.isa c2146e4e20cd30c35b7ff4f4cd15c953663cdc4d src/arch/arm/isa/insts/macromem.isa c2146e4e20cd30c35b7ff4f4cd15c953663cdc4d src/arch/arm/isa/insts/misc.isa c2146e4e20cd30c35b7ff4f4cd15c953663cdc4d Diff: http://reviews.gem5.org/r/3318/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
