changeset faf5195f6ca7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=faf5195f6ca7
description:
scons: Add missing override to appease clang
Make clang happy...again.
diffstat:
src/arch/hsail/insts/branch.hh | 60 ++++++++++----------
src/arch/hsail/insts/mem.hh | 107 ++++++++++++++++++-----------------
src/arch/mips/tlb.hh | 8 +-
src/arch/power/tlb.hh | 8 +-
src/arch/sparc/system.hh | 4 +-
src/cpu/checker/cpu.hh | 4 +-
src/dev/mips/malta.hh | 8 +-
src/dev/mips/malta_cchip.hh | 4 +-
src/dev/mips/malta_io.hh | 6 +-
src/dev/sparc/dtod.hh | 4 +-
src/dev/sparc/iob.hh | 6 +-
src/dev/sparc/mm_disk.hh | 4 +-
src/mem/ruby/system/DMASequencer.hh | 8 +-
13 files changed, 117 insertions(+), 114 deletions(-)
diffs (truncated from 801 to 300 lines):
diff -r 64e862d3758f -r faf5195f6ca7 src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hh Thu Feb 18 10:50:16 2016 -0500
+++ b/src/arch/hsail/insts/branch.hh Tue Feb 23 03:27:20 2016 -0500
@@ -51,7 +51,7 @@
class BrnInstBase : public HsailGPUStaticInst
{
public:
- void generateDisassembly();
+ void generateDisassembly() override;
Brig::BrigWidth8_t width;
TargetType target;
@@ -69,43 +69,43 @@
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
bool unconditionalJumpInstruction() override { return true; }
- bool isVectorRegister(int operandIndex) {
+ bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister();
}
- bool isCondRegister(int operandIndex) {
+ bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isCondRegister();
}
- bool isScalarRegister(int operandIndex) {
+ bool isScalarRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isScalarRegister();
}
- bool isSrcOperand(int operandIndex) {
+ bool isSrcOperand(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return true;
}
- bool isDstOperand(int operandIndex) {
+ bool isDstOperand(int operandIndex) override {
return false;
}
- int getOperandSize(int operandIndex) {
+ int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize();
}
- int getRegisterIndex(int operandIndex) {
+ int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}
- int getNumOperands() {
+ int getNumOperands() override {
return 1;
}
- void execute(GPUDynInstPtr gpuDynInst);
+ void execute(GPUDynInstPtr gpuDynInst) override;
};
template<typename TargetType>
@@ -166,7 +166,7 @@
class CbrInstBase : public HsailGPUStaticInst
{
public:
- void generateDisassembly();
+ void generateDisassembly() override;
Brig::BrigWidth8_t width;
CRegOperand cond;
@@ -186,47 +186,47 @@
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
- void execute(GPUDynInstPtr gpuDynInst);
+ void execute(GPUDynInstPtr gpuDynInst) override;
// Assumption: Target is operand 0, Condition Register is operand 1
- bool isVectorRegister(int operandIndex) {
+ bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.isVectorRegister();
else
return false;
}
- bool isCondRegister(int operandIndex) {
+ bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.isCondRegister();
else
return true;
}
- bool isScalarRegister(int operandIndex) {
+ bool isScalarRegister(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex)
return target.isScalarRegister();
else
return false;
}
- bool isSrcOperand(int operandIndex) {
+ bool isSrcOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == 0)
return true;
return false;
}
// both Condition Register and Target are source operands
- bool isDstOperand(int operandIndex) {
+ bool isDstOperand(int operandIndex) override {
return false;
}
- int getOperandSize(int operandIndex) {
+ int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.opSize();
else
return 1;
}
- int getRegisterIndex(int operandIndex) {
+ int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.regIndex();
@@ -235,7 +235,7 @@
}
// Operands = Target, Condition Register
- int getNumOperands() {
+ int getNumOperands() override {
return 2;
}
};
@@ -335,7 +335,7 @@
class BrInstBase : public HsailGPUStaticInst
{
public:
- void generateDisassembly();
+ void generateDisassembly() override;
ImmOperand<uint32_t> width;
TargetType target;
@@ -354,33 +354,33 @@
bool unconditionalJumpInstruction() override { return true; }
- void execute(GPUDynInstPtr gpuDynInst);
- bool isVectorRegister(int operandIndex) {
+ void execute(GPUDynInstPtr gpuDynInst) override;
+ bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister();
}
- bool isCondRegister(int operandIndex) {
+ bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isCondRegister();
}
- bool isScalarRegister(int operandIndex) {
+ bool isScalarRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isScalarRegister();
}
- bool isSrcOperand(int operandIndex) {
+ bool isSrcOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return true;
}
- bool isDstOperand(int operandIndex) { return false; }
- int getOperandSize(int operandIndex) {
+ bool isDstOperand(int operandIndex) override { return false; }
+ int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize();
}
- int getRegisterIndex(int operandIndex) {
+ int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}
- int getNumOperands() { return 1; }
+ int getNumOperands() override { return 1; }
};
template<typename TargetType>
diff -r 64e862d3758f -r faf5195f6ca7 src/arch/hsail/insts/mem.hh
--- a/src/arch/hsail/insts/mem.hh Thu Feb 18 10:50:16 2016 -0500
+++ b/src/arch/hsail/insts/mem.hh Tue Feb 23 03:27:20 2016 -0500
@@ -102,50 +102,52 @@
addr.init(op_offs, obj);
}
- int numSrcRegOperands() { return(this->addr.isVectorRegister()); }
- int numDstRegOperands() { return dest.isVectorRegister(); }
- bool isVectorRegister(int operandIndex)
+ int numSrcRegOperands() override
+ { return(this->addr.isVectorRegister()); }
+ int numDstRegOperands() override
+ { return dest.isVectorRegister(); }
+ bool isVectorRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isVectorRegister() :
this->addr.isVectorRegister());
}
- bool isCondRegister(int operandIndex)
+ bool isCondRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isCondRegister() :
this->addr.isCondRegister());
}
- bool isScalarRegister(int operandIndex)
+ bool isScalarRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isScalarRegister() :
this->addr.isScalarRegister());
}
- bool isSrcOperand(int operandIndex)
+ bool isSrcOperand(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex > 0)
return(this->addr.isVectorRegister());
return false;
}
- bool isDstOperand(int operandIndex) {
+ bool isDstOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return(operandIndex == 0);
}
- int getOperandSize(int operandIndex)
+ int getOperandSize(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize());
}
- int getRegisterIndex(int operandIndex)
+ int getRegisterIndex(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() :
this->addr.regIndex());
}
- int getNumOperands()
+ int getNumOperands() override
{
if (this->addr.isVectorRegister())
return 2;
@@ -348,52 +350,53 @@
}
}
- int numSrcRegOperands() { return(this->addr.isVectorRegister()); }
- int numDstRegOperands() { return dest.isVectorRegister(); }
- int getNumOperands()
+ int numSrcRegOperands() override
+ { return(this->addr.isVectorRegister()); }
+ int numDstRegOperands() override { return dest.isVectorRegister(); }
+ int getNumOperands() override
{
if (this->addr.isVectorRegister())
return 2;
else
return 1;
}
- bool isVectorRegister(int operandIndex)
+ bool isVectorRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isVectorRegister() :
this->addr.isVectorRegister());
}
- bool isCondRegister(int operandIndex)
+ bool isCondRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isCondRegister() :
this->addr.isCondRegister());
}
- bool isScalarRegister(int operandIndex)
+ bool isScalarRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isScalarRegister() :
this->addr.isScalarRegister());
}
- bool isSrcOperand(int operandIndex)
+ bool isSrcOperand(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex > 0)
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