[gem5-dev] changeset in gem5: mem, cpu: Add assertions to snoop invalidatio...

[Stephan Diestelhorst]

changeset 6668387fa488 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6668387fa488
description:
        mem, cpu: Add assertions to snoop invalidation logic

        This patch adds assertions that enforce that only invalidating snoops
        will ever reach into the logic that tracks in-order load completion and
        also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds
        some comments to MSHR::replaceUpgrades().

diffstat:

 src/arch/arm/locked_mem.hh  |  7 +++++--
 src/cpu/o3/lsq_unit_impl.hh |  3 +++
 src/mem/cache/blk.hh        |  2 ++
 src/mem/cache/mshr.hh       |  6 ++++++
 4 files changed, 16 insertions(+), 2 deletions(-)

diffs (66 lines):

diff -r a80884911971 -r 6668387fa488 src/arch/arm/locked_mem.hh
--- a/src/arch/arm/locked_mem.hh        Sun Jul 19 15:03:30 2015 -0500
+++ b/src/arch/arm/locked_mem.hh        Mon Aug 10 11:25:52 2015 +0100
@@ -64,7 +64,10 @@
 inline void
 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 {
-    DPRINTF(LLSC,"%s:  handleing snoop for address: %#x locked: %d\n",
+    // Should only every see invalidations / direct writes
+    assert(pkt->isInvalidate() || pkt->isWrite());
+
+    DPRINTF(LLSC,"%s:  handling snoop for address: %#x locked: %d\n",
             xc->getCpuPtr()->name(),pkt->getAddr(),
             xc->readMiscReg(MISCREG_LOCKFLAG));
     if (!xc->readMiscReg(MISCREG_LOCKFLAG))
@@ -74,7 +77,7 @@
     // If no caches are attached, the snoop address always needs to be masked
     Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
 
-    DPRINTF(LLSC,"%s:  handleing snoop for address: %#x locked addr: %#x\n",
+    DPRINTF(LLSC,"%s:  handling snoop for address: %#x locked addr: %#x\n",
             xc->getCpuPtr()->name(),snoop_addr, locked_addr);
     if (locked_addr == snoop_addr) {
         DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
diff -r a80884911971 -r 6668387fa488 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh       Sun Jul 19 15:03:30 2015 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh       Mon Aug 10 11:25:52 2015 +0100
@@ -435,6 +435,9 @@
 void
 LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
 {
+    // Should only ever get invalidations in here
+    assert(pkt->isInvalidate());
+
     int load_idx = loadHead;
     DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
 
diff -r a80884911971 -r 6668387fa488 src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh      Sun Jul 19 15:03:30 2015 -0500
+++ b/src/mem/cache/blk.hh      Mon Aug 10 11:25:52 2015 +0100
@@ -335,6 +335,8 @@
      */
     bool checkWrite(PacketPtr pkt)
     {
+        assert(pkt->isWrite());
+
         // common case
         if (!pkt->isLLSC() && lockList.empty())
             return true;
diff -r a80884911971 -r 6668387fa488 src/mem/cache/mshr.hh
--- a/src/mem/cache/mshr.hh     Sun Jul 19 15:03:30 2015 -0500
+++ b/src/mem/cache/mshr.hh     Mon Aug 10 11:25:52 2015 +0100
@@ -149,7 +149,13 @@
         bool isReset() const { return !needsWritable && !hasUpgrade; }
         void add(PacketPtr pkt, Tick readyTime, Counter order,
                  Target::Source source, bool markPending);
+
+        /**
+         * Convert upgrades to the equivalent request if the cache line they
+         * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
+         * Used to rejig ordering between targets waiting on an MSHR. */
         void replaceUpgrades();
+
         void clearDownstreamPending();
         bool checkFunctional(PacketPtr pkt);
         void print(std::ostream &os, int verbosity,
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