> On March 15, 2016, 8:54 p.m., Andreas Sandberg wrote: > > src/arch/arm/ArmISA.py, line 55 > > <http://reviews.gem5.org/r/3377/diff/1/?file=54099#file54099line55> > > > > This is a bit scary since the PMU is needs to know which interrupt to > > use and that's generally defined by the platform code (see > > src/dev/arm/ReaView.py). Ideally, this device should live with the other > > platform devices, but I'm not sure how we would wire it to the ISA in that > > case.
I had actually tried to hook the pmu up from other code rather than changing the NULL here, which wasn't successful. If anyone knows a good way how to do it I'll be more than happy to. - Bjoern A. ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3377/#review8088 ----------------------------------------------------------- On March 15, 2016, 5 p.m., Bjoern A. Zeeb wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3377/ > ----------------------------------------------------------- > > (Updated March 15, 2016, 5 p.m.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > arm,dev,config: always preent the PMU but add option to enable > > Always attach the PMU to an ARM core but do not enable the > relevant instructions/events unless asked for by setting the > new command line option --pmu. > > Note: this should work fine for 1 core systems, for multi-core > there might be an interrupt delivery issue still (SPI vs. PPI). > Consider this as an example for people who want to work on it > as the question has previously come up on the mailing lists on > how to hook this up. > > > Diffs > ----- > > configs/common/Options.py 2fd64ea0a7cb > configs/example/fs.py 2fd64ea0a7cb > src/arch/arm/ArmISA.py 2fd64ea0a7cb > > Diff: http://reviews.gem5.org/r/3377/diff/ > > > Testing > ------- > > > Thanks, > > Bjoern A. Zeeb > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
