Hi all, I have 15 patches currently posted to ReviewBoard (listed below). They've all been awaiting review for over three weeks, but most have no feedback at all. Just a gentle reminder to provide feedback as we'd like to commit these soon (before this time next week).
http://reviews.gem5.org/r/3339/ cpu: Add SMT support to MinorCPU http://reviews.gem5.org/r/3341/ cpu: Fix BTB threading oversight http://reviews.gem5.org/r/3343/ cpu: Add instruction opclass histogram to minor http://reviews.gem5.org/r/3344/ cpu: Add an indirect branch target predictor http://reviews.gem5.org/r/3345/ cpu: Implement per-thread GHRs http://reviews.gem5.org/r/3351/ sim: Add additional debug information when draining http://reviews.gem5.org/r/3352/ misc: Add secondary dot output for DVFS domains http://reviews.gem5.org/r/3342/ mem: Remove threadId from memory request class http://reviews.gem5.org/r/3350/ sim: Fix clock_domain unserialization http://reviews.gem5.org/r/3358/ cpu: Query CPU for inst executed from Python http://reviews.gem5.org/r/3361/ sim: Adding thermal model support http://reviews.gem5.org/r/3362/ sim: Thermal support for Linux http://reviews.gem5.org/r/3365/ sim: Adding support for power models http://reviews.gem5.org/r/3364/ pwr: Low-power idle power state for idle CPUs http://reviews.gem5.org/r/3363/ pwr: Add power states to ClockedObject Thanks! Curtis IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
