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(Updated April 14, 2016, 10:42 p.m.) Review request for Default. Changes ------- Updated again to work with latest head (rev 11443:df24b9af42c7) Repository: gem5 Description (updated) ------- Changeset 11444:8a1419dbbfa6 --------------------------- mem: implement x86 locked accesses in timing-mode classic cache Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, use a combination of clearing permission bits and leaving an MSHR in place to prevent accesses & snoops from touching a locked block between the read and write parts of an locked RMW sequence. Diffs (updated) ----- src/mem/cache/cache.cc df24b9af42c72606f1fa8e5aa0502b53e81ea176 src/mem/cache/mshr.hh df24b9af42c72606f1fa8e5aa0502b53e81ea176 src/mem/packet.hh df24b9af42c72606f1fa8e5aa0502b53e81ea176 src/mem/packet.cc df24b9af42c72606f1fa8e5aa0502b53e81ea176 Diff: http://reviews.gem5.org/r/2691/diff/ Testing ------- Thanks, Steve Reinhardt _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
