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Nice! Looks pretty straightforward, esp. compared to the previous patch... src/cpu/o3/comm.hh (line 70) <http://reviews.gem5.org/r/3458/#comment7128> put '{}' on a separate line. ';' is unnecessary src/cpu/o3/comm.hh (line 71) <http://reviews.gem5.org/r/3458/#comment7129> blank line between methods (here & below) src/cpu/o3/comm.hh (line 75) <http://reviews.gem5.org/r/3458/#comment7130> again optional, but consider !(*this==that) src/cpu/o3/comm.hh (line 77) <http://reviews.gem5.org/r/3458/#comment7131> When do we need ordering of PhysRegIds? Please add a comment here explaining why this is needed. Also, why not just compare _flatIdx? src/cpu/o3/comm.hh (line 83) <http://reviews.gem5.org/r/3458/#comment7132> see my comment on the previous patch on restructuring this expression. - Steve Reinhardt On April 28, 2016, 5 a.m., Andreas Sandberg wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3458/ > ----------------------------------------------------------- > > (Updated April 28, 2016, 5 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11465:cd2aa6d3d60f > --------------------------- > cpu: Physical register structural + flat indexing > > Mimic the changes done on the architectural register indexes on the > physical register indexes. This is specific to the O3 model. The > structure, called PhysRegId, contains a register class, a register > index and a flat register index. The flat register index is kept > because it is useful in some cases where the type of register is not > important (dependency graph and scoreboard for example). Instead of > directly using the structure, most of the code is working with a const > PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId objects > are stored in the regFile. > > Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667 > Signed-off-by: Andreas Sandberg <[email protected]> > > > Diffs > ----- > > src/cpu/o3/cpu.cc d9e32a851e2e > src/cpu/o3/dyn_inst.hh d9e32a851e2e > src/cpu/o3/dyn_inst_impl.hh d9e32a851e2e > src/cpu/o3/free_list.hh d9e32a851e2e > src/cpu/o3/iew_impl.hh d9e32a851e2e > src/cpu/o3/inst_queue_impl.hh d9e32a851e2e > src/cpu/o3/probe/elastic_trace.cc d9e32a851e2e > src/cpu/o3/regfile.hh d9e32a851e2e > src/cpu/o3/regfile.cc d9e32a851e2e > src/cpu/o3/rename.hh d9e32a851e2e > src/cpu/o3/rename_impl.hh d9e32a851e2e > src/cpu/o3/rename_map.hh d9e32a851e2e > src/cpu/o3/rename_map.cc d9e32a851e2e > src/cpu/o3/scoreboard.hh d9e32a851e2e > src/cpu/o3/scoreboard.cc d9e32a851e2e > src/cpu/base_dyn_inst.hh d9e32a851e2e > src/cpu/o3/comm.hh d9e32a851e2e > src/cpu/o3/cpu.hh d9e32a851e2e > > Diff: http://reviews.gem5.org/r/3458/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Sandberg > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
