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Ship it! Looks reasonable, thanks. - Curtis Dunham On May 20, 2016, 10:09 p.m., Jason Lowe-Power wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3474/ > ----------------------------------------------------------- > > (Updated May 20, 2016, 10:09 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11482:51dec612f11b > --------------------------- > cpu, x86: Allow the TLB to be warmed up before CPU switch > > Previously, before a CPU was switched out, the TLB was always flushed > Now, we first call takeOverFrom with the TLB. We only flush > the TLB right before the CPU is switched in. > This changeset also contains the needed code for x86 to > takeOverFrom with the TLB, similar changes may be needed for the ARM > architecture. > With this changeset, when you switch from atomic to timing mode the > TLB is warm. > > > Diffs > ----- > > src/arch/x86/tlb.hh fc247b9c42b6 > src/arch/x86/tlb.cc fc247b9c42b6 > src/cpu/base.cc fc247b9c42b6 > > Diff: http://reviews.gem5.org/r/3474/diff/ > > > Testing > ------- > > > Thanks, > > Jason Lowe-Power > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
