Hi Mohammad, The actual updating of the memory is already done by that time (by calling AbstractMemory::access). Thus, there is no need to worry about the data at this point, only timing.
Andreas On 09/06/2016, 08:01, "gem5-dev on behalf of Mohammad Alian" <[email protected] on behalf of [email protected]> wrote: >Hi, > >In mem_ctrl.cc, when a write request arrives at the memory controller, in >"addToWriteQueue" function we check if an existing request to the same >address is in the writeQueue to whether we can merge them together: > >bool merged = isInWriteQueue.find(burstAlign(addr)) != > isInWriteQueue.end(); > >But I cannot see any piece of code which actually merge these two >requests. >Shouldn't the later request override the data of the earlier request? > >Thanks, >Mohammad >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
