changeset dd6dfd38b6c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dd6dfd38b6c2
description:
stats: Update stats to reflect ARM changes
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 646 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
| 3120 +++++-----
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
| 34 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
| 18 +-
28 files changed, 2105 insertions(+), 2105 deletions(-)
diffs (truncated from 6484 to 300 lines):
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
Mon Jun 20 15:51:31 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
Tue Jun 21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2847227406000 #
Number of ticks simulated
final_tick 2847227406000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 262523 #
Simulator instruction rate (inst/s)
-host_op_rate 317894 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5870765699 #
Simulator tick rate (ticks/s)
-host_mem_usage 664268 #
Number of bytes of host memory used
-host_seconds 484.98 #
Real time elapsed on the host
+host_inst_rate 166460 #
Simulator instruction rate (inst/s)
+host_op_rate 201569 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3722516357 #
Simulator tick rate (ticks/s)
+host_mem_usage 624360 #
Number of bytes of host memory used
+host_seconds 764.87 #
Real time elapsed on the host
sim_insts 127319545 #
Number of instructions simulated
sim_ops 154173476 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -456,7 +456,7 @@
system.cpu0.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3513 #
Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3449 #
Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1354 #
Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1959 #
Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -540,7 +540,7 @@
system.cpu0.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2216 #
Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2152 #
Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -1406,7 +1406,7 @@
system.cpu1.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2060 #
Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1996 #
Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 164 #
Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 367 #
Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -1495,7 +1495,7 @@
system.cpu1.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1166 #
Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1102 #
Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
Mon Jun 20 15:51:31 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
Tue Jun 21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2858505242500 #
Number of ticks simulated
final_tick 2858505242500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 258042 #
Simulator instruction rate (inst/s)
-host_op_rate 311992 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6591883972 #
Simulator tick rate (ticks/s)
-host_mem_usage 625700 #
Number of bytes of host memory used
-host_seconds 433.64 #
Real time elapsed on the host
+host_inst_rate 152549 #
Simulator instruction rate (inst/s)
+host_op_rate 184443 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3896990443 #
Simulator tick rate (ticks/s)
+host_mem_usage 585436 #
Number of bytes of host memory used
+host_seconds 733.52 #
Real time elapsed on the host
sim_insts 111897168 #
Number of instructions simulated
sim_ops 135292215 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -418,7 +418,7 @@
system.cpu.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4350 #
Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 4286 #
Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 1526 #
Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 1789 #
Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -498,7 +498,7 @@
system.cpu.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2992 #
Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2928 #
Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Mon Jun 20 15:51:31 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Tue Jun 21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2832862976500 #
Number of ticks simulated
final_tick 2832862976500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 118022 #
Simulator instruction rate (inst/s)
-host_op_rate 143150 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2956132692 #
Simulator tick rate (ticks/s)
-host_mem_usage 626728 #
Number of bytes of host memory used
-host_seconds 958.30 #
Real time elapsed on the host
+host_inst_rate 69451 #
Simulator instruction rate (inst/s)
+host_op_rate 84238 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1739551926 #
Simulator tick rate (ticks/s)
+host_mem_usage 585172 #
Number of bytes of host memory used
+host_seconds 1628.50 #
Real time elapsed on the host
sim_insts 113100501 #
Number of instructions simulated
sim_ops 137180951 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -410,7 +410,7 @@
system.cpu.checker.dtb.flush_tlb_mva 1834 #
Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 4283 #
Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 4219 #
Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 1622 #
Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -480,7 +480,7 @@
system.cpu.checker.itb.flush_tlb_mva 1834 #
Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 2976 #
Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries 2912 #
Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -588,7 +588,7 @@
system.cpu.dtb.flush_tlb_mva 1834 #
Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4317 #
Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 4253 #
Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 362 #
Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2060 #
Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -690,7 +690,7 @@
system.cpu.itb.flush_tlb_mva 1834 #
Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3089 #
Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3025 #
Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Mon Jun 20 15:51:31 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Tue Jun 21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2825959731500 #
Number of ticks simulated
final_tick 2825959731500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 153141 #
Simulator instruction rate (inst/s)
-host_op_rate 185771 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3602870624 #
Simulator tick rate (ticks/s)
-host_mem_usage 666712 #
Number of bytes of host memory used
-host_seconds 784.36 #
Real time elapsed on the host
+host_inst_rate 99061 #
Simulator instruction rate (inst/s)
+host_op_rate 120168 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2330545961 #
Simulator tick rate (ticks/s)
+host_mem_usage 626024 #
Number of bytes of host memory used
+host_seconds 1212.57 #
Real time elapsed on the host
sim_insts 120118276 #
Number of instructions simulated
sim_ops 145712235 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -485,7 +485,7 @@
system.cpu0.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3541 #
Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3477 #
Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 219 #
Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2242 #
Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -584,7 +584,7 @@
system.cpu0.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2345 #
Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2281 #
Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -1729,7 +1729,7 @@
system.cpu1.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2051 #
Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1987 #
Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 47 #
Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 392 #
Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -1830,7 +1830,7 @@
system.cpu1.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1194 #
Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1130 #
Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Mon Jun
20 15:51:31 2016 +0100
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt Tue Jun
21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2832862976500 #
Number of ticks simulated
final_tick 2832862976500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 159277 #
Simulator instruction rate (inst/s)
-host_op_rate 193189 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3989457396 #
Simulator tick rate (ticks/s)
-host_mem_usage 626716 #
Number of bytes of host memory used
-host_seconds 710.09 #
Real time elapsed on the host
+host_inst_rate 93807 #
Simulator instruction rate (inst/s)
+host_op_rate 113780 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2349621266 #
Simulator tick rate (ticks/s)
+host_mem_usage 586720 #
Number of bytes of host memory used
+host_seconds 1205.67 #
Real time elapsed on the host
sim_insts 113100501 #
Number of instructions simulated
sim_ops 137180951 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -444,7 +444,7 @@
system.cpu.dtb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4317 #
Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 4253 #
Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 362 #
Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2060 #
Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 #
Number of TLB faults due to domain restrictions
@@ -546,7 +546,7 @@
system.cpu.itb.flush_tlb_mva 917 #
Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 #
Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 #
Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3089 #
Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3025 #
Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 #
Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 #
Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 #
Number of TLB faults due to domain restrictions
diff -r 479d053f05af -r dd6dfd38b6c2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Mon Jun 20 15:51:31 2016 +0100
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Tue Jun 21 16:42:04 2016 +0100
@@ -4,11 +4,11 @@
sim_ticks 2823728611500 #
Number of ticks simulated
final_tick 2823728611500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 403127 #
Simulator instruction rate (inst/s)
-host_op_rate 488997 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9263554618 #
Simulator tick rate (ticks/s)
-host_mem_usage 632872 #
Number of bytes of host memory used
-host_seconds 304.82 #
Real time elapsed on the host
+host_inst_rate 236626 #
Simulator instruction rate (inst/s)
+host_op_rate 287030 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5437492370 #
Simulator tick rate (ticks/s)
+host_mem_usage 592088 #
Number of bytes of host memory used
+host_seconds 519.31 #
Real time elapsed on the host
sim_insts 122881667 #
Number of instructions simulated
sim_ops 149056790 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -313,12 +313,12 @@
system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% #
Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% #
Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3632 #
Writes before turning the bus around for reads
-system.physmem.totQLat 1343217000 #
Total ticks spent queuing
-system.physmem.totMemAccLat 3470892000 #
Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1343214500 #
Total ticks spent queuing
+system.physmem.totMemAccLat 3470889500 #
Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 567380000 #
Total ticks spent in databus transfers
-system.physmem.avgQLat 11837.01 #
Average queueing delay per DRAM burst
+system.physmem.avgQLat 11836.99 #
Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 #
Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30587.01 #
Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30586.99 #
Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.57 #
Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.56 #
Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.57 #
Average system read bandwidth in MiByte/s
@@ -340,28 +340,28 @@
system.physmem_0.readEnergy 459334200 #
Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 228024720 #
Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 179708830080 #
Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 71920019610 #
Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1621544120250 #
Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1874104093725 #
Total energy per rank (pJ)
-system.physmem_0.averagePower 667.482603 #
Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2641247036500 #
Time in different power states
+system.physmem_0.actBackEnergy 71920006785 #
Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1621544131500 #
Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1874104092150 #
Total energy per rank (pJ)
+system.physmem_0.averagePower 667.482602 #
Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2641247054000 #
Time in different power states
system.physmem_0.memoryStateTime::REF 91875680000 #
Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 #
Time in different power states
-system.physmem_0.memoryStateTime::ACT 18345228000 #
Time in different power states
+system.physmem_0.memoryStateTime::ACT 18345210500 #
Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 #
Time in different power states
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