Hi Giray, If an instruction is unimplemented, you should see a warning printed to stderr. Something like "warn: instruction 'prefetch_nta' unimplemented". This warning came from one of my simulations ;).
As far as the speedup goes, gem5 is not known for its accuracy compared to real systems. Even if the instruction was implemented correctly in the ISA, that doesn't mean that it's implemented in the core correctly and that it's implemented in the cache correctly. (Feel free to substitute "high performance" for "correct" in the previous sentence). Hope this helps, Jason On Thu, Jun 30, 2016 at 2:24 AM Abdullah Giray Yaglikci < [email protected]> wrote: > Abdullah Giray Yaglikci <agyaglikci@...> writes: > > > > Hi All, > > > > This is a general question about a specific issue. When we compile our > > workloads with a cross compiler, cross compiler actually does not know > the > > details about the gem5 as a target platform. Let's assume that the cross > > compiler generated some instructions which were not implemented in the > gem5. > > During the full system simulation, when gem5 fetches these unimplemented > > instructions, what would be the reaction? Does it just run nop or fail or > > return warning or something else? > > > > In my specific case, I'm using _mm_prefetch function which produces > > PREFETCHT0 instruction for x86 full system simulation. I'm not sure if > gem5 > > executes this instruction properly as I always observe slow down on gem5 > > while the same workload speeds up like 8% on a real system. Therefore, I > > need to double check that gem5 executes this instruction or replaces it > with > > a load instruction not with a nop. > > > > I'm aware that prefetch instructions are considered as unnecessary by > some > > of you as the hardware prefetchers are good enough. Thus I wanted to ask > > this question in a more generalized form. I believe that this question > will > > help me (and other newbies) to understand how gem5 works better. > > > > Could someone illuminate the issue please? > > > > Thanks in advance > > > > Giray > > > > _______________________________________________ > > gem5-dev mailing list > > gem5-dev <at> gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev > > > > > To make it more clear, here is a test about the prefetch instructon: > https://gist.github.com/agyaglikci/f1099625f18909d1eb06aa7151484712 > > As I mentioned it in the comments, even though the compiler generates > prefetcht0 instruction, the gem5 stats say that no prefetch instruction was > executed. This can be related with the missing speedup in my other > simulation. > > Any comments, suggestions are really appreciated. > > Thanks > > Giray > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
