Apologies all, it was brought to my attention that there were two versions of this on ReviewBoard and the one I was managing had no feedback.
http://reviews.gem5.org/r/3545/ vs http://reviews.gem5.org/r/3565/ We will post a fixup to this commit once all feedback on the latter is resolved. Curtis -----Original Message----- From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Gabor Dozsa Sent: Thursday, July 21, 2016 5:21 PM To: gem5-...@m5sim.org Subject: [gem5-dev] changeset in gem5: arm, config: Add an example ARM big.LITTLE(tm... changeset 2eae1dfaa791 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=2eae1dfaa791 description: arm, config: Add an example ARM big.LITTLE(tm) configuration script An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> diffstat: configs/example/arm/devices.py | 144 ++++++++++++++++ configs/example/arm/fs_bigLITTLE.py | 308 ++++++++++++++++++++++++++++++++++++ system/arm/dt/Makefile | 10 +- system/arm/dt/armv8_big_little.dts | 147 +++++++++++++++++ 4 files changed, 607 insertions(+), 2 deletions(-) diffs (truncated from 642 to 300 lines): diff -r 91e95eb78191 -r 2eae1dfaa791 configs/example/arm/devices.py --- /dev/nullThu Jan 01 00:00:00 1970 +0000 +++ b/configs/example/arm/devices.pyThu Jul 21 17:19:16 2016 +0100 @@ -0,0 +1,144 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual # +property including but not limited to intellectual property relating # +to a hardware implementation of the functionality of the software # +licensed hereunder. You may use the software subject to the license # +terms below provided that you ensure that this notice is replicated # +unmodified and in its entirety in all distributions of the software, # +modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without # +modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright # +notice, this list of conditions and the following disclaimer; # +redistributions in binary form must reproduce the above copyright # +notice, this list of conditions and the following disclaimer in the # +documentation and/or other materials provided with the distribution; # +neither the name of the copyright holders nor the names of its # +contributors may be used to endorse or promote products derived from # +this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg +# Gabor Dozsa + +# System components used by the bigLITTLE.py configuration script + +import m5 +from m5.objects import * +m5.util.addToPath('../../common') +from Caches import * + +class L1I(L1_ICache): + hit_latency = 1 + response_latency = 1 + mshrs = 4 + tgts_per_mshr = 8 + size = '48kB' + assoc = 3 + + +class L1D(L1_DCache): + hit_latency = 2 + response_latency = 1 + mshrs = 16 + tgts_per_mshr = 16 + size = '32kB' + assoc = 2 + write_buffers = 16 + + +class WalkCache(PageTableWalkerCache): + hit_latency = 4 + response_latency = 4 + mshrs = 6 + tgts_per_mshr = 8 + size = '1kB' + assoc = 8 + write_buffers = 16 + + +class L2(L2Cache): + hit_latency = 12 + response_latency = 5 + mshrs = 32 + tgts_per_mshr = 8 + size = '1MB' + assoc = 16 + write_buffers = 8 + clusivity='mostly_excl' + + +class L3(Cache): + size = '16MB' + assoc = 16 + hit_latency = 20 + response_latency = 20 + mshrs = 20 + tgts_per_mshr = 12 + clusivity='mostly_excl' + + +class MemBus(SystemXBar): + badaddr_responder = BadAddr(warn_access="warn") + default = Self.badaddr_responder.pio + + +class SimpleSystem(LinuxArmSystem): + cache_line_size = 64 + + voltage_domain = VoltageDomain(voltage="1.0V") + clk_domain = SrcClockDomain(clock="1GHz", + voltage_domain=Parent.voltage_domain) + + realview = VExpress_GEM5_V1() + + gic_cpu_addr = realview.gic.cpu_addr + flags_addr = realview.realview_io.pio_addr + 0x30 + + membus = MemBus() + + intrctrl = IntrControl() + terminal = Terminal() + vncserver = VncServer() + + iobus = IOXBar() + # CPUs->PIO + iobridge = Bridge(delay='50ns') + # Device DMA -> MEM + dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions) + + _pci_devices = 0 + _clusters = [] + _cpus = [] + + def attach_pci(self, dev): + dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) + self._pci_devices += 1 + self.realview.attachPciDevice(dev, self.iobus) + + def connect(self): + self.iobridge.master = self.iobus.slave + self.iobridge.slave = self.membus.master + + self.dmabridge.master = self.membus.slave + self.dmabridge.slave = self.iobus.master + + self.gic_cpu_addr = self.realview.gic.cpu_addr + self.realview.attachOnChipIO(self.membus, self.iobridge) + self.realview.attachIO(self.iobus) + self.system_port = self.membus.slave diff -r 91e95eb78191 -r 2eae1dfaa791 configs/example/arm/fs_bigLITTLE.py --- /dev/nullThu Jan 01 00:00:00 1970 +0000 +++ b/configs/example/arm/fs_bigLITTLE.pyThu Jul 21 17:19:16 2016 +0100 @@ -0,0 +1,308 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual # +property including but not limited to intellectual property relating # +to a hardware implementation of the functionality of the software # +licensed hereunder. You may use the software subject to the license # +terms below provided that you ensure that this notice is replicated # +unmodified and in its entirety in all distributions of the software, # +modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without # +modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright # +notice, this list of conditions and the following disclaimer; # +redistributions in binary form must reproduce the above copyright # +notice, this list of conditions and the following disclaimer in the # +documentation and/or other materials provided with the distribution; # +neither the name of the copyright holders nor the names of its # +contributors may be used to endorse or promote products derived from # +this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabor Dozsa +# Andreas Sandberg + +# This is an example configuration script for full system simulation of +# a generic ARM bigLITTLE system. + + +import argparse +import os +import sys +import m5 +from m5.objects import * + +m5.util.addToPath("../../common") +import SysPaths +import CpuConfig + +import devices + + +default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb' +default_kernel = 'vmlinux4.3.aarch64' +default_disk = 'aarch64-ubuntu-trusty-headless.img' +default_rcs = 'bootscript.rcS' + +default_mem_size= "2GB" + +def createSystem(kernel, mem_mode, bootscript, disks=[]): + sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel), + readfile=bootscript, + mem_mode=mem_mode, + machine_type="DTOnly") + + mem_region = sys.realview._mem_regions[0] + sys.mem_ctrls = SimpleMemory( + range=AddrRange(start=mem_region[0], size=default_mem_size)) + sys.mem_ctrls.port = sys.membus.master + + sys.connect() + + # Attach disk images + if disks: + def cow_disk(image_file): + image = CowDiskImage() + image.child.image_file = SysPaths.disk(image_file) + return image + + sys.disk_images = [ cow_disk(f) for f in disks ] + sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img)) + for img in sys.disk_images ] + for dev in sys.pci_vio_block: + sys.attach_pci(dev) + + sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary) + + return sys + + +class CpuCluster(SubSystem): + def addCPUs(self, cpu_config, num_cpus, cpu_clock, cpu_voltage="1.0V"): + try: + self._cluster_id + m5.util.panic("CpuCluster.addCPUs() must be called exactly once") + except AttributeError: + pass + + assert num_cpus > 0 + system = self._parent + self._cluster_id = len(system._clusters) + system._clusters.append(self) + self._config = cpu_config + + self.voltage_domain = VoltageDomain(voltage=cpu_voltage) + self.clk_domain = SrcClockDomain(clock=cpu_clock, + + voltage_domain=self.voltage_domain) + + cpu_class = cpu_config['cpu'] + self.cpus = [ cpu_class(cpu_id=len(system._cpus) + idx, + clk_domain=self.clk_domain) + for idx in range(num_cpus) ] + + for cpu in self.cpus: + cpu.createThreads() + cpu.createInterruptController() + cpu.socket_id = self._cluster_id + system._cpus.append(cpu) + + def createCache(self, key): + try: + return self._config[key]() + except KeyError: + return None + + def addL1(self): + self._cluster_id + for cpu in self.cpus: + l1i = self.createCache('l1i') + l1d = self.createCache('l1d') + iwc = self.createCache('wcache') + dwc = self.createCache('wcache') + cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc) + + def addL2(self, clk_domain): + self._cluster_id + self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) + #self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain, + #snoop_filter=NULL) + self.l2 = self._config['l2']() + for cpu in self.cpus: + cpu.connectAllPorts(self.toL2Bus) + self.toL2Bus.master = self.l2.cpu_side + + def connectMemSide(self, bus): _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. 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