changeset d6cfd0be73b2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d6cfd0be73b2
description:
arm: Fix secure state checking in various places
Faults that could potentially be routed to the hypervisor checked
whether or not they were in a secure state without checking if security
was enabled or not. This caused faults not to be routed correctly. This
patch causes secure state checking to first ask if security is enabled.
Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
diffstat:
src/arch/arm/faults.cc | 13 ++++++-------
src/arch/arm/interrupts.cc | 4 ++--
src/arch/arm/interrupts.hh | 8 +++-----
3 files changed, 11 insertions(+), 14 deletions(-)
diffs (108 lines):
diff -r afe051c345e9 -r d6cfd0be73b2 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Tue Aug 02 10:38:02 2016 +0100
+++ b/src/arch/arm/faults.cc Tue Aug 02 10:38:02 2016 +0100
@@ -1116,7 +1116,7 @@
toHyp |= (stage2 ||
( (source == DebugEvent) && hdcr.tde &&
(cpsr.mode != MODE_HYP)) ||
( (source == SynchronousExternalAbort) && hcr.tge &&
(cpsr.mode == MODE_USER))
- ) && !inSecureState(scr, cpsr);
+ ) && !inSecureState(tc);
return toHyp;
}
@@ -1182,7 +1182,7 @@
((source == AlignmentFault) ||
(source == SynchronousExternalAbort))
)
- ) && !inSecureState(scr, cpsr);
+ ) && !inSecureState(tc);
return toHyp;
}
@@ -1272,7 +1272,7 @@
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// Determine whether IRQs are routed to Hyp mode.
- toHyp = (!scr.irq && hcr.imo && !inSecureState(scr, cpsr)) ||
+ toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
(cpsr.mode == MODE_HYP);
return toHyp;
}
@@ -1311,7 +1311,7 @@
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// Determine whether IRQs are routed to Hyp mode.
- toHyp = (!scr.fiq && hcr.fmo && !inSecureState(scr, cpsr)) ||
+ toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
(cpsr.mode == MODE_HYP);
return toHyp;
}
@@ -1380,10 +1380,9 @@
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
- CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
- toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) ||
- (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr));
+ toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
+ (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
return toHyp;
}
diff -r afe051c345e9 -r d6cfd0be73b2 src/arch/arm/interrupts.cc
--- a/src/arch/arm/interrupts.cc Tue Aug 02 10:38:02 2016 +0100
+++ b/src/arch/arm/interrupts.cc Tue Aug 02 10:38:02 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009, 2012-2013 ARM Limited
+ * Copyright (c) 2009, 2012-2013, 2016 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -65,7 +65,7 @@
else
scr = tc->readMiscReg(MISCREG_SCR_EL3);
- bool is_secure = inSecureState(scr, cpsr);
+ bool is_secure = inSecureState(tc);
switch(int_type) {
case INT_FIQ:
diff -r afe051c345e9 -r d6cfd0be73b2 src/arch/arm/interrupts.hh
--- a/src/arch/arm/interrupts.hh Tue Aug 02 10:38:02 2016 +0100
+++ b/src/arch/arm/interrupts.hh Tue Aug 02 10:38:02 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -141,10 +141,9 @@
return false;
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
- SCR scr = tc->readMiscReg(MISCREG_SCR);
bool isHypMode = cpsr.mode == MODE_HYP;
- bool isSecure = inSecureState(scr, cpsr);
+ bool isSecure = inSecureState(tc);
bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
@@ -229,13 +228,12 @@
HCR hcr = tc->readMiscReg(MISCREG_HCR);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
- SCR scr = tc->readMiscReg(MISCREG_SCR);
// Calculate a few temp vars so we can work out if there's a pending
// virtual interrupt, and if its allowed to happen
// ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
bool isHypMode = cpsr.mode == MODE_HYP;
- bool isSecure = inSecureState(scr, cpsr);
+ bool isSecure = inSecureState(tc);
bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
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