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Review request for Default. Repository: gem5 Description ------- mem: Modify drain to ensure banks and power are idled Add constraint that all ranks have to be in PWR_IDLE before signaling drain complete This will ensure that the banks are all closed and the rank has exited any low-power states. On suspend, update the power stats to sync the DRAM power logic The logic maintains the location of the signalDrainDone method, which is still triggered from either: 1) Read response event 2) Next request event This ensures that the drain will complete in the READ bus state and minimizes the changes required. Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1 Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com> Diffs ----- src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 Diff: http://reviews.gem5.org/r/3600/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
